DS92LV2411 Datasheet, PDF (8/40 Pages) National Semiconductor (TI) – 5-50MHz 24-Bit Channel Link II Serializer and Deserializer

Pin Name
Pin #
I/O, Type Description
CONFIG[1:0] 10 [DO22], STRAP 00: Control Signal Filter DISABLED
9 [DO23] I, LVCMOS 01: Control Signal Filter ENABLED
w/ pull-down 10: Reverse compatibility mode to interface with the DS90UR241 or DS99R241
11: Reverse compatibility mode to interface with the DS90C241
LF_MODE
12 [DO20] STRAP SSCG Low Frequency Mode
I, LVCMOS Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE
w/ pull-down (X).
LF_MODE = 1, SSCG in low frequency mode (CLK = 5-20 MHz)
LF_MODE = 0, SSCG in high frequency mode (CLK = 20-50 MHz)
This can also be controlled by I2C register access.
OS_CLKOUT 11 [DO21] STRAP Output CLKOUT Slew Select
I, LVCMOS OS_CLKOUT = 1, Increased CLKOUT slew rate
w/ pull-down OS_CLKOUT = 0, Normal CLKOUT slew rate (default)
This can also be controlled by I2C register access.
OS_DATA
14 [DO19] STRAP Output DO[23:0], CO1, CO2, CO3 Slew Select
I, LVCMOS OS_DATA = 1, Increased DO slew rate
w/ pull-down OS_DATA = 0, Normal DO slew rate (default)
This can also be controlled by I2C register access.
OP_LOW
42 [PASS] STRAP Outputs held LOW when LOCK = 1
I, LVCMOS NOTE: Do not use any other strap options with this strap function enabled
w/ pull-down OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH.
NOTE: Before the device is powered up, the outputs are in TRI-STATE™
See Figure 24 and Figure 25
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default)
This can also be controlled by I2C register access.
OSS_SEL
17 [DO18] STRAP Output Sleep State Select
I, LVCMOS OSS_SEL is used in conjunction with PDB to determine the state of the outputs in Power
w/ pull-down Down (Sleep). (See Table 7).
NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW = 1
This can also be controlled by I2C register access.
RFB
18 [DO17] STRAP Clock Output Strobe Edge Select
I, LVCMOS RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
w/ pull-down RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
This can also be controlled by I2C register access.
EQ[3:0]
20 [DO15], STRAP Receiver Input Equalization
21 [DO14], I, LVCMOS (See Table 4).
22 [DO13], w/ pull-down This can also be controlled by I2C register access.
23 [DO12]
OSC_SEL[2:0] 26 [DO10], STRAP Oscillator Selectl
27 [DO9], I, LVCMOS (See Table 8 and Table 9).
28 [DO8] w/ pull-down This can also be controlled by I2C register access.
SSC[3:0]
34 [DO6], STRAP Spread Spectrum Clock Generation (SSCG) Range Select
35 [DO5], I, LVCMOS (See Table 5 and Table 6).
36 [DO4], w/ pull-down This can also be controlled by I2C register access.
37 [DO3]
MAP_SEL[1:0] 40[D],
STRAP Bit mapping reverse compatibility / DS90UR241 Options
41 [D] I, LVCMOS Pin or Register Control
w/ pull-down Default setting is b'00.
Control and Configuration
PDB
59
I, LVCMOS Power Down Mode Input
w/ pull-down PDB = 1, Des is enabled (normal operation).
Refer to “Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by Table
7. Control Registers are RESET.
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