DS92LV2411 Datasheet, PDF (37/40 Pages) National Semiconductor (TI) – 5-50MHz 24-Bit Channel Link II Serializer and Deserializer

Figure 33 shows a typical connection diagram of the
DS92LV2412 Des in pin/strap control mode for a 24-bit ap-
plication. The CML inputs utilize 0.1 µF coupling capacitors to
the line and the receiver provides internal termination. Bypass
capacitors are placed near the power supply pins. At a mini-
mum, seven 0.1 µF capacitors and two 4.7 µF capacitors
should be used for local device bypassing. System GPO
(General Purpose Output) signals control the PDB and the
BISTEN pins. In this application the RFB pin is tied Low to
strobe the data on the falling edge of the CLKOUT.
Since the device in the Pin/STRAP mode, four 10 kΩ pull up
resistors are used on the parallel output bus to select the de-
sired device features. CFEN is set to 1 for Normal Mode with
Control Signal Filter enabled, this is accomplished with the
STRAP pull-up on DO23. The receiver input equalizer is also
enabled and set to provide 7.5 dB of gain, this is accomplished
with EQ[3:0] set to 1001'b with STRAP pull ups on DO12 and
DO15. To reduce parallel bus EMI, the SSCG feature is en-
abled and set to fmod = CLK/2168 and ±1% with SSC[3:0] set
to 0010'b and a STRAP pull-up on DO4. The desired features
are set with the use of the four pull up resistors.
The interface to the target display is with 3.3V LVCMOS lev-
els, thus the VDDIO pin is connected to the 3.3 V rail. The
optional Serial Bus Control is not used in this example, thus
the SCL, SDA and ID[x] pins are left open. A delay cap is
placed on the PDB signal to delay the enabling of the device
until power is stable.
FIGURE 33. DS92LV2412 Typical Connection Diagram — Pin Control
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