LMH6601_14 Datasheet, PDF (8/37 Pages) National Semiconductor (TI) – LMH6601/LMH6601Q 250 MHz, 2.4V CMOS Operational Amplifier with Shutdown

LMH6601, LMH6601-Q1
SNOSAK9E – JUNE 2006 – REVISED MARCH 2013
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2.7V ELECTRICAL CHARACTERISTICS (continued)
Single Supply with V_S = 2.7V, A_V = +2, R_F = 604Ω, SD tied to V⁺, V_OUT = V_S/2, R_L = 150Ω to V^− unless otherwise specified.
Boldface limits apply at temperature extremes. ⁽¹⁾
Symbol
Parameter
Condition
Min ⁽²⁾
Typ ⁽²⁾ Max ⁽²⁾
Units
−PSRR
Negative Power Supply Rejection DC
Ratio
56
69
53
dB
CMRR
CMVR
Common Mode Rejection Ratio
Input Voltage Range
DC
CMRR > 50 dB
57
77
dB
52
V^− -0.20
–
V⁺ -1.5
V
I_CC
Supply Current
VOH1
Output High Voltage
(Relative to V⁺)
Normal Operation
V_OUT = V_S/2
Shutdown
SD tied to ≤ 0.27V ⁽⁵⁾
R_L = 150Ω to V^–
9.0
10.6
12.5
mA
100
nA
–260
–420
–200
VOH2
VOH3
VOL1
Output Low Voltage
(Relative to V^–)
R_L = 75Ω to V_S/2
R_L = 10 kΩ to V^–
R_L = 150Ω to V^–
–200
mV
–50
–10
100
+4
+45
+125
VOL2
VOL3
R_L = 75Ω to V_S/2
R_L = 10 kΩ to V^–
+125
mV
+4
+45
125
I_O
I_O_1
Output Current
V_OUT ≤ 0.6V from Respective Source
25
Supply
Sink
62
mA
V_OUT = V_S/2, V_ID = ±18 mV Source
25
(6)
Sink
35
Load
Output Load Rating
THD < −30 dBc, f = 200 kHz, R_L tied to
40
Ω
V_S/2, V_OUT = 2.2 V_PP
R_O_Enable Output Resistance
Enabled, A_V = +1
0.2
Ω
R_O_Disabled Output Resistance
Shutdown
>100
MΩ
C_O_Disabled Output Capacitance
Shutdown
5.6
pF
Miscellaneous Performance
VDMAX
Voltage Limit for Disable (Pin 5) See ⁽⁵⁾
0
0.27
V
VDMIN
Voltage Limit for Enable (Pin 5)
See ⁽⁵⁾
2.43
2.7
V
I_i
Logic Input Current (Pin 5)
SD = 2.7V ⁽⁵⁾
4
pA
V_{_glitch}
Turn-on Glitch
1.2
V
T_on
Turn-on Time
5.2
µs
T_off
Turn-off Time
760
ns
Isolation_OFF Off Isolation
1 MHz, R_L = 1 kΩ
60
dB
(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%
of total supply voltage away from either supply rail.
(6) “V_ID” is input differential voltage (input overdrive).
8
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