LMH6601_14 Datasheet, PDF (6/37 Pages) National Semiconductor (TI) – LMH6601/LMH6601Q 250 MHz, 2.4V CMOS Operational Amplifier with Shutdown

LMH6601, LMH6601-Q1
SNOSAK9E – JUNE 2006 – REVISED MARCH 2013
www.ti.com
3.3V ELECTRICAL CHARACTERISTICS (continued)
Single Supply with V_S= 3.3V, A_V = +2, R_F = 604Ω, SD tied to V⁺, V_OUT = V_S/2, R_L = 150Ω to V^− unless otherwise specified.
Boldface limits apply at temperature extremes. ⁽¹⁾
Symbol
Parameter
Condition
Min ⁽²⁾
Typ ⁽²⁾ Max ⁽²⁾
Units
I_B
Input Bias Current
I_OS
Input Offset Current
See ⁽⁴⁾
See ⁽⁴⁾
5
50
pA
2
25
pA
R_IN
Input Resistance
0V ≤ V_IN ≤ 1.8V
15
TΩ
C_IN
Input Capacitance
1.4
pF
+PSRR
Positive Power Supply Rejection DC
Ratio
61
80
dB
51
−PSRR
Negative Power Supply Rejection DC
Ratio
57
72
dB
52
CMRR
CMVR
Common Mode Rejection Ratio
Input Voltage Range
DC
CMRR > 50 dB
58
73
dB
55
V^− -0.20
–
V⁺ -1.5
V
I_CC
Supply Current
VOH1
Output High Voltage
(Relative to V⁺)
Normal Operation
V_OUT = V_S/2
Shutdown
SD tied to ≤ 0.33V ⁽⁵⁾
R_L = 150Ω to V^–
9.2
11
13
mA
100
nA
–210
–360
–190
VOH2
VOH3
VOL1
Output Low Voltage
(Relative to V^–)
R_L = 75Ω to V_S/2
R_L = 10 kΩ to V^−
R_L = 150Ω to V^–
–190
mV
–50
–10
–100
+4
+45
+125
VOL2
VOL3
R_L = 75Ω to V_S/2
R_L = 10 kΩ to V^–
+105
mV
+4
+45
+125
I_O
Output Current
V_OUT < 0.6V from Respective Source
50
Supply
Sink
75
mA
I_O_1
V_OUT = V_S/2, V_ID = ±18 mV ⁽⁶⁾
±75
Load
Output Load Rating
THD < −30 dBc, f = 200 kHz,
R_L tied to V_S/2, V_OUT = 2.6 V_PP
25
Ω
R_O_Enabled Output Resistance
Enabled, A_V = +1
0.2
Ω
R_O_Disabled Output Resistance
Shutdown
>100
MΩ
C_O_Disabled Output Capacitance
Shutdown
5.6
pF
Miscellaneous Performance
VDMAX
Voltage Limit for Disable (Pin 5) See ⁽⁵⁾
0
0.33
V
VDMIN
Voltage Limit for Enable (Pin 5)
See ⁽⁵⁾
2.97
3.3
V
I_i
Logic Input Current (Pin 5)
SD = 3.3V ⁽⁵⁾
8
pA
V_{_glitch}
Turn-on Glitch
1.6
V
T_on
Turn-on Time
3.5
µs
T_off
Turn-off Time
500
ns
Isolation_OFF Off Isolation
1 MHz, R_L = 1 kΩ
60
dB
(4) This parameter is ensured by design and/or characterization and is not tested in production.
(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%
of total supply voltage away from either supply rail.
(6) “V_ID” is input differential voltage (input overdrive).
6
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