DS92LV3221 Datasheet, PDF (8/24 Pages) National Semiconductor (TI) – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

Serializer Input Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
t_CIP
TxCLKIN Period
t_CIH
TxCLKIN High Time
20 MHz – 50 MHz
t_TCIL
TxCLKIN Low Time
t_CIT
TxCLKIN Transition Time
t_JIT
TxCLKIN Jitter
20 MHz – 50 MHz
Figure 5
20 MHz – 50 MHz
Figure 4
Min
20
0.45 x
t_CIP
0.45 x
t_CIP
Typ
t_CIP
0.5 x t_CIP
0.5 x t_CIP
Max
50
0.55 x
t_CIP
0.55 x
t_CIP
0.5
1.2
±100
Units
ns
ns
ns
ns
ps_P-P
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Units
t_LLHT
t_LHLT
t_STC
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
TxIN[31:0] Setup to TxCLKIN
No pre-emphasis
Figure 3
IOVDD = 1.71V to 1.89V
Figure 5
IOVDD = 3.135V to 3.465V
350
ps
350
ps
0
ns
0
t_HTC
TxIN[31:0] Hold from TxCLKIN
IOVDD = 1.71V to 1.89V
2.5
ns
IOVDD = 3.135V to 3.465V
2.25
t_PLD
Serializer PLL Lock Time
Figure 7
t_LZD
Data Output LOW to TRI-STATE® (Note 4)
Delay
t_HZD
Data Output TRI-STATE® to HIGH (Note 4)
Delay
t_SD
Serializer Propagation Delay -
f = 50 MHz,
Latency
R_FB = H,
PRE = OFF,
Figure 6
f = 50 MHz,
R_FB = L,
PRE = OFF,
4400 x 5000 x
t_CIP
t_CIP
ns
5
10
ns
5
10
ns
4.5 t_CIP +
6.77
4.5 t_CIP + 4.5 t_CIP + 4.5 t_CIP + _ns
5.63
7.09
9.29
f = 20 MHz,
R_FB = H,
PRE = OFF,
4.5 t_CIP + 4.5 t_CIP + 4.5 t_CIP +
6.57
8.74 10.74
t_LVSKD
Λ_STXBW
δ_STX
LVDS Output Skew
Jitter Transfer Function -3 dB
Bandwidth
Serializer Jitter Transfer Function
Peaking
LVDS differential output channel-to-
channel skew
f = 50 MHz
Figure 13
f = 50 MHz
30
500
ps
2.8
MHz
0.3
dB
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