DS92LV3221 Datasheet, PDF (6/24 Pages) National Semiconductor (TI) – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V_DD)
LVCMOS Input
Voltage
LVCMOS Output
Voltage
LVDS Deserializer Input
Voltage
−0.3V to +4V
−0.3V to (V_DD +0.3V)
−0.3V to (V_DD +0.3V)
−0.3V to +3.9V
LVDS Driver Output
Voltage
−0.3V to +3.9V
Junction Temperature
+125°C
Storage Temperature
−65°C to +150°C
Lead Temperature
(Soldering, 4 seconds)
+260°C
Maximum Package Power Dissipation Capacity
Package Derating:
1/θ_JA °C/W above +25°C
  θ_JA
35.7 °C/W*
  θ_JC
12.6 °C/W
*4 Layer JEDEC
ESD Rating (HBM)
>4 kV
Recommended Operating
Conditions
Supply Voltage (V_DD)
Supply Voltage (IOV_DD)
(SER ONLY)
3.3V I/O Interface
1.8V I/O Interface
Operating Free Air
Temperature (T_A)
Input Clock Rate
Tolerable Supply Noise
Min
3.135
3.135
1.71
−40
20
Nom
3.3
3.3
1.8
+25
Max
3.465
3.465
1.89
+85
50
100
Units
V
V
V
°C
MHz
mV_P-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3)
Symbol
Parameter
Conditions
Min
Typ
LVCMOS DC SPECIFICATIONS
V_IH
High Level Input Voltage
Tx: IOV_DD = 1.71V to 1.89V
Tx: IOV_DD = 3.135V to 3.465V
Rx
0.65 x
IOV_DD
2.0
V_IL
Low Level Input Voltage
Tx: IOV_DD = 1.71V to 1.89V
GND
Tx: IOV_DD = 3.135V to 3.465V
Rx
V_CL
Input Clamp Voltage
I_IN
Input Current
V_OH
High Level Output Voltage
V_OL
Low Level Output Voltage
I_OS
Output Short Circuit Current
I_OZ
TRI-STATE® Output Current
SERIALIZER LVDS DC SPECIFICATIONS
I_CL = −18 mA
Tx: V_IN = 0V or 3.465V(1.89V)
IOV_DD = 3.465V(1.89V)
Rx: V_IN = 0V or 3.465V
I_OH = −2mA
I_OH = −2mA
V_OUT = 0V
PDB = 0V,
V_OUT = 0V or V_DD
V_OD
Output Differential Voltage
No pre-emphasis, VSEL = L
(VSEL = H)
ΔV_OD
Output Differential Voltage Unbalance VSEL = L,
No pre-emphasis
V_OS
Offset Voltage
VSEL = L,
No pre-emphasis
ΔV_OS
Offset Voltage Unbalance
VSEL = L,
No pre-emphasis
GND
−10
−10
2.4
GND
−10
−0.8
3.0
0.33
−22
350
(629)
440
(850)
1
1.00 1.25
4
Max Units
IOV_DD +
0.3
V
V_DD
0.35 x
IOV_DD
V
0.8
−1.5
V
+10
µA
+10
V_DD
V
0.5
V
−40 mA
+10
μA
525
(1000)
mV_P-P
50
mV_P-P
1.50
V
50
mV
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