DS92LV3221 Datasheet, PDF (3/24 Pages) National Semiconductor (TI) – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3221 Serializer Pin Descriptions
Pin # Pin Name I/O, Type
Description
LVCMOS PARALLEL INTERFACE PINS
10–8,
5–1,
64–57,
52–51,
48–44.
41–33
TxIN[31:29],
TxIN[28:24],
TxIN[23:16],
TxIN[15:14],
TxIN[13:9],
TxIN[8:0]
I, LVCMOS
Serializer Parallel Interface Data Input Pins.
11
TxCLKIN
I, LVCMOS Serializer Parallel Interface Clock Input Pin. Strobe edge set by R_FB configuration pin.
CONTROL AND CONFIGURATION PINS
12
PDB
I, LVCMOS
Serializer Power Down Bar (ACTIVE LOW)
PDB = L; Device Disabled, Differential serial outputs are put into TRI-STATE® stand-by mode,
PLL is shutdown
PDB = H; Device Enabled
19
PRE
I, LVCMOS PRE-emphasis level select pin
PRE = (RPRE > 12kΩ); Imax = [(1.2/R) x 20 x 2], Rmin = 12kΩ.
PRE = H or floating; pre-emphasis is disabled.
14
R_FB
I, LVCMOS
Rising/Falling Bar Clock Edge Select
R_FB = H; Rising Edge,
R_FB = L; Falling Edge
20
VSEL
I, LVCMOS
VOD (Differential Output Voltage) Llevel Select
VSEL = L; Low Swing,
VSEL = H; High Swing
13
BISTEN
I, LVCMOS BIST Enable
BISTEN = L; BIST OFF, (default), normal operating mode.
BISTEN = H; BIST Enabled (ACTIVE HIGH)
15, 16 RSVD
I, LVCMOS Reserved — MUST BE TIED LOW
21, 22, NC
23, 24
Do Not Connect, leave pins floating
LVDS SERIAL INTERFACE PINS
28, 30 TxOUT[1:0]+ O, LVDS
Serializer LVDS Non-Inverted Outputs(+)
27, 29 TxOUT[1:0]- O, LVDS
Serializer LVDS Inverted Outputs(-)
POWER / GROUND PINS
7, 18, VDD
32, 42
VDD
Digital Voltage supply, 3.3V
6, 17, VSS
31, 43
GND
Digital ground
53, 56 VDDPLL
VDD
Analog Voltage supply, PLL POWER, 3.3V
54, 55 VSSPLL
GND
Analog ground, PLL GROUND
26
VDDA
VDD
Analog Voltage supply
25
VSSA
GND
Analog ground
49
IOVDD
VDD
Digital IO Voltage supply Connect to 1.8V typ for 1.8V LVCMOS interface Connect to 3.3V typ
for 3.3V LVCMOS interface
50
IOVSS
GND
Digital IO ground
3
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