DS92LV3221 Datasheet, PDF (7/24 Pages) National Semiconductor (TI) – 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer

Symbol
Parameter
Conditions
Min
Typ
Max
I_OS
Output Short Circuit Current
TxOUT[1:0] = 0V,
PDB = V_DD,
VSEL = L,
No pre-emphasis
−2
−5
TxOUT[1:0] = 0V,
PDB = V_DD,
VSEL = H,
No pre-emphasis
−6
−10
I_OZ
TRI-STATE® Output Current
PDB = 0V,
TxOUT[1:0] = 0V OR V_DD
−15
±1
+15
PDB = V_DD,
TxOUT[1:0] = 0V OR V_DD
−15
±1
+15
R_T
Output Termination
Internal differential output termination
between differential pairs
90
100
130
SERIALIZER SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
I_DDTD
Serializer (Tx) Total Supply Current
(includes load current)
f= 50 MHz,
CHECKER BOARD pattern
VSEL = H,
PRE = OFF
120
145
f= 50 MHz,
CHECKER BOARD pattern
VSEL = H,
120
145
RPRE = 12 kΩ
f= 50 MHz,
RANDOM pattern
VSEL = H,
PRE = OFF
115
135
f= 50 MHz,
RANDOM pattern
VSEL = H,
115
135
RPRE = 12 kΩ
I_DDTZ
Serializer Supply Current
Power-down
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
2
50
DESERIALIZER LVDS DC SPECIFICATIONS
V_TH
Differential Threshold High Voltage V_CM = +1.8V
+50
V_TL
Differential Threshold Low Voltage
−50
R_T
Input Termination
Internal differential output termination
between differential pairs
90
100
130
I_IN
Input Current
V_IN = +2.4V, V_DD = 3.6V
±100
V_IN = 0V, V_DD = 3.6V
±100
DESERIALIZER SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
±250
±250
f = 50 MHz,
C_L = 8 pF,
CHECKER BOARD pattern
145
185
f = 50 MHz,
C_L = 8 pF,
RANDOM pattern
122
140
I_DDRZ
Deserializer Supply Current Power- PDB = 0V
down
(All other LVCMOS Inputs = 0V,
100
RxIN[1:0](P/N) = 0V)
Units
mA
µA
µA
Ω
mA
µA
mV
mV
Ω
µA
µA
mA
µA
7
www.national.com