COPCH942C Datasheet, PDF (8/26 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k

COP620C/COP622C/COP640C/COP642C
Absolute Maximum Ratings (Note 13)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V_CC)
Voltage at any Pin
6V
−0.3V to V_CC + 0.3V
Total Current into V_CC Pin (Source)
Total Current out of GND Pin (Sink)
40 mA
48 mA
Storage Temperature Range
−65˚C to +140˚C
Note 13: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
DC Electrical Characteristics
COP62XC, COP64XC; −55˚C ≤ T_A ≤ +125˚C unless otherwise specified
Parameter
Condition
Operating Voltage
Power Supply Ripple (Note 14)
Peak to Peak
Supply Current (Note 15)
CKI = 10 MHz
CKI = 4 MHz
HALT Current (Note 16)
Input Levels
V_CC = 5.5V, tc = 1 µs
V_CC = 5.5V, tc = 2.5 µs
V_CC = 5.5V, CKI = 0 MHz
RESET , CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current
G Port Input Hysteresis
V_CC = 5.5V
V_CC = 4.5V, V_IN = 0V
Output Current Levels
D Outputs
Source
Sink
All Others
V_CC = 4.5V, V_OH = 3.8V
V_CC = 4.5V, V_OL = 1.0V
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
V_CC = 4.5V, V_OH = 3.2V
V_CC = 4.5V, V_OH = 3.8V
V_CC = 4.5V, V_OL = 0.4V
Allowable Sink/Source
Current Per Pin
D Outputs (Sink)
All Others
Maximum Input Current (Room Temp)
Without Latchup (Note 18)
Room Temp
RAM Retention Voltage, Vr
500 ns Rise and Fall Time
(Min)
Input Capacitance
Load Capacitance on D2
Min
4.5
0.9 V_CC
0.7 V_CC
−5
−35
−0.35
9
−9
−0.35
1.4
−5.0
2.5
Typ
Max
5.5
0.1 V_CC
6.0
4
<10
30
0.1 V_CC
0.2 V_CC
+5
−300
0.35 V_CC
−120
+5.0
12
2.5
±100
7
1000
Units
V
V
mA
mA
µA
V
V
V
V
µA
µA
V
mA
mA
µA
mA
mA
µA
mA
mA
mA
V
pF
pF
Note 14: Rate of voltage change must be less than 0.5V/ms.
Note 15: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 16: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V_CC, L and G0 — G5 configured
as outputs and set high. The D port set to zero.
Note 17: Except pin G7: +100 mA, −25 mA (COP620C only). Sampled and not 100% tested. Pins G6 and RESET are designed with a high voltage input network
for factory testing. These pins allow input voltages greater than V_CC and the pins will have sink current to V_CC when biased at voltages greater than V_CC (the pins
do not have source current when biased at a voltage below V_CC). The effective resistance to V_CC is 750Ω (typical). These two pins will not latch up. The voltage at
the pins must be limited to less than 14V.
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