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| COPCH942C Datasheet, PDF (19/26 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k | |||
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Instruction Set (Continued)
Instruction Set (Continued)
SBIT
Set bit
RBIT
Reset bit
IFBIT
If bit
X
LD A
LD mem
LD Reg
X
X
LD A
LD A
LD M
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
Exchange A with memory
Load A with memory
Load Direct memory Immed.
Load Register memory Immed.
Exchange A with memory [B]
Exchange A with memory [X]
Load A with memory [B]
Load A with memory [X]
Load Memory Immediate
Clear A
Increment A
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHT THRU C
Swap nibbles of A
Set C
Reset C
If C
If not C
Jump absolute long
Jump absolute
Jump relative short
Jump subroutine long
Jump subroutine
Jump indirect
Return from subroutine
Return and Skip
Return from Interrupt
Generate an interrupt
No operation
1 to bit,
Mem (bit= 0 to 7 immediate)
0 to bit,
Mem
If bit,
Mem is true, do next instr.
A â Mem
A â MemI
Mem â Imm
Reg â Imm
A â [B] (B â B±1)
A â [X] (X â X±1)
A â [B] (B â B±1)
A â [X] (X â X±1)
[B] â Imm (B â B±1)
Aâ0
AâA+1
AâAâ1
A â ROM(PU,A)
A â BCD correction (follows ADC, SUBC)
C â A7 â ⦠â A0 â C
A7 ⦠A4 â A3 ⦠A0
C â 1, HC â 1
C â 0, HC â 0
If C is true, do next instruction
If C is not true, do next instruction
PC â ii (ii = 15 bits, 0 to 32k)
PC11..0 â i (i = 12 bits)
PC â PC + r (r is â31 to +32, not 1)
[SP] â PL,[SP-1] â PU,SP-2,PC â ii
[SP] â PL,[SP-1] â PU,SP-2,PC11.. 0 â i
PL â ROM(PU,A)
SP+2,PL â [SP],PU â [SP-1]
SP+2,PL â [SP],PU â [SP-1],Skip next instruction
SP+2,PL â [SP],PU â [SP-1],GIE â 1
[SP] â PL,[SPâ1] â PU,SP-2,PC â 0FF
PC â PC + 1
19
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