COPCH942C Datasheet, PDF (21/26 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k

Instruction Execution Time
Most instructions are single byte (with immediate addressing
mode instruction taking two bytes).
Most single instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per
Instruction
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
[B]
Direct
1/1
3/4
1/1
3/4
1/1
3/4
1/1
3/4
1/1
3/4
1/1
3/4
1/1
3/4
Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
[B]
Direct
Immed.
IFGT
1/1
3/4
2/2
IFBNE
1/1
DRSZ
1/3
SBIT
1/1
3/4
RBIT
1/1
3/4
IFBIT
1/1
3/4
The following table shows the instructions assigned to un-
used opcodes. This table is for information only. The opera-
tions performed are subject to change without notice. Do not
use these opcodes.
Unused
Opcode
60
61
62
63
67
8C
99
9F
A7
A8
Instruction
NOP
NOP
NOP
NOP
NOP
RET
NOP
LD [B], #i
X A, [B]
NOP
Unused
Opcode
A9
AF
B1
B4
B5
B7
B9
BF
Instruction
NOP
LD A, [B]
C → HC
NOP
NOP
X A, [X]
NOP
LD A, [X]
Memory Transfer Instructions
X A,*
LD A,*
LD B,Imm
LD B,Imm
LD Mem,Imm
LD Reg,Imm
Register
Indirect
[B] [X]
1/1 1/3
1/1 1/3
2/2
Direct
2/3
2/3
3/3
Note 20: * = > Memory location addressed by B or X or directly.
Immed.
2/2
1/1
2/3
2/3
Register Indirect
Auto Incr & Decr
[B+, B−] [X+, X−]
1/2
1/3
1/2
1/3
2/2
(If B < 16)
(If B > 15)
Instructions Using A & C
CLRA
1/1
INCA
1/1
DECA
1/1
LAID
1/3
DCORA
1/1
RRCA
1/1
SWAPA
1/1
SC
1/1
RC
1/1
IFC
1/1
IFNC
1/1
Transfer of Control Instructions
JMPL
3/4
JMP
2/3
JP
1/3
JSRL
3/5
JSR
2/5
JID
1/3
RET
1/5
RETSK
1/5
RETI
1/5
INTR
1/7
NOP
1/1
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