COPCH942C Datasheet, PDF (18/26 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k

Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
Contents
COP820C Family
00 to 2F On Chip RAM Bytes
30 to 7F Unused RAM Address Space (Reads as all
Ones)
COP840C Family
00 to 6F On Chip RAM Bytes
70 to 7F Unused RAM Address Space (Reads as all
Ones)
COP820C and COP840C Families
80 to BF Expansion Space for on Chip EERAM
C0 to CF Expansion Space for I/O and Registers
D0 to DF On Chip I/O and Registers
D0
Port L Data Register
D1
Port L Configuration Register
D2
Port L Input Pins (Read Only)
D3
Reserved for Port L
D4
Port G Data Register
D5
Port G Configuration Register
D6
Port G Input Pins (Read Only)
Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Registers
A 8-bit Accumulator register
B 8-bit Address register
X 8-bit Address register
SP 8-bit Stack pointer register
PC 15-bit Program counter register
PU upper 7 bits of PC
PL lower 8 bits of PC
C 1-bit of PSW register for carry
HC Half Carry
GIE 1-bit of PSW register for global interrupt enable
Instruction Set
ADD
ADC
add
add with carry
SUBC
subtract with carry
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
Logical AND
Logical OR
Logical Exclusive-OR
IF equal
IF greater than
IF B not equal
Decrement Reg. ,skip if zero
Address
Contents
COP820C and COP840C Families
D7
Port I Input Pins (Read Only)
D8–DB Reserved for Port C
DC
Port D Data Register
DD–DF Reserved for Port D
E0 to EF On Chip Functions and Registers
E0–E7 Reserved for Future Parts
E8
Reserved
E9
MICROWIRE/PLUS Shift Register
EA
Timer Lower Byte
EB
Timer Upper Byte
EC
Timer Autoload Register Lower Byte
ED
Timer Autoload Register Upper Byte
EE
CNTRL Control Register
EF
PSW Register
F0 to FF On Chip RAM Mapped as Registers
FC
X Register
FD
SP Register
FE
B Register
Reading unused memory locations below 7FH will return all
ones. Reading other unused memory locations will return
undefined data.
Symbols
[B] Memory indirectly addressed by B register
[X] Memory indirectly addressed by X register
Mem Direct address memory or [B]
MemI Direct address memory or [B] or Immediate data
Imm 8-bit Immediate data
Reg Register memory: addresses F0 to FF (Includes B, X
and SP)
Bit Bit number (0 to 7)
← Loaded with
↔ Exchanged with
A ← A + MemI
A ← A + MemI + C, C ← Carry
HC ← Half Carry
A ← A + MemI +C, C ← Carry
HC ← Half Carry
A ← A and MemI
A ← A or MemI
A ← A xor MemI
Compare A and MemI, Do next if A = MemI
Compare A and MemI, Do next if A > MemI
Do next if lower 4 bits of B ≠ Imm
Reg ← Reg − 1, skip if Reg goes to 0
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