NS486SXL Datasheet, PDF (7/26 Pages) National Semiconductor (TI) – Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

Connection Diagram
Note: In the above figure and in the following tables, all active low signals are shown with an overbar.
FIGURE 3. NS486SXL Package Pinout Diagram
The NS486SXL single chip controller is provided in a com-
pact 132-pin, industry standard JEDEC PQFP package. The
following tables detail the Symbol, Type, and Description of
each pin. The tables divide the pins into functional groups as
follows: Bus Interface Unit Pins, DRAM Control Pins, Power
Pins, Reset Logic Pins, Auxiliary Processor Interface Pins,
Test Pins, Interrupt Control Pins, Real Time Clock Pins, Os-
cillator Pins, UART/IrDA Pins, Timer Pins, 3-Wire Serial I/O
Pins, External Bus Master, General Purpose Chip Select
Pins, and Reconfigurable I/O Pins. Twenty-eight I/O pins are
multipurpose. In their standard modes, they perform specific
I/O controller functions. When those particular I/O functions
are not required in the system, however, those pins can be
reprogrammed to become general purpose, bidirectionsl I/O
lines.
Note: In the above figure and in the following tables, all active low signals are
shown with an overbar.
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DS100121-4
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