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NS486SXL Datasheet, PDF (21/26 Pages) National Semiconductor (TI) – Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems
ISA-like Bus Cycles Timing Specification (Continued)
TABLE 19. No Command Delay ISA-like Bus Specifications (Continued)
Symbol
Parameter
Formula
Min
Max
tRCDH
tWCDH
tWCVD
tWCS
Read CMD Data Hold Time
Write CMD Data Hold Time
Write CMD to Valid Data
Write Command Setup Time
1.0T +
0.5T +
0
−25
5
−20
Note 12: The value of (Wait) in the above formulae, is the number of programmed wait states associated with that access cycle (default value is 7, but may be pro-
grammed to 0–7).
TABLE 20. One Programmed Command Delay ISA-like Bus Specifications
Symbol
Parameter
Formula
Min
Max
tAHCD
tASCD
tCDPW
tCHCD
tCSCD
tDOFF
tRCAT
tRCDH
tWCDH
tWCVD
tWCS
Address Hold Time from CMD
Address Setup Time to CMD
Command Pulse Width
Chip Select Hold Time from CMD
Chip Select Setup Time to CMD
Read Data TRI-STATE
Read CMD Data Access Time
Read CMD Data Hold Time
Write CMD Data Hold Time
Write Valid Data to CMD (Note 14)
Write Command Setup Time
1.0T +
−20
2.0T +
−20
1.0T + (Wait)T +
−10
1.0T +
−25
2.0T +
−40
1.0T +
−25
1.0T + (Wait)T +
−30
0
1.0T +
−25
1.0T +
−5
0.5T +
−20
Note 13: The value of (Wait) in the above formulae, is the number of programmed wait states associated with that access cycle (default value is 7, but may be pro-
grammed to 0–7).
Note 14: For this case Valid Write Data Sets-up to the leading edge of the Command Strobe.
Ready Feedback Timing Specifications
FIGURE 10. Ready Feedback Timing Diagram
DS100121-15
TABLE 21. Ready Signal Timing Specifications
Symbol
Parameter
Formula
Min
Max
tRACD
tRDYH
tRDYL
RDY Active to CMD Rising
RDY Hold Time from CMD
CMD to RDY Inactive Feedback
(E_RDY)T +
0
0
1.0T + (Wait)T +
−30
Note 15: The value of (Wait) in the above formulae, is the number of programmed wait states associated with that access cycle (default value is 7, but may be pro-
grammed to 0–7). The value of (E_RDY) in the above formulae, is the number of programmed extended ready states associated with every access cycle (default
number is 2, but may be programmed to 0–2).
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