NS486SXL Datasheet, PDF (19/26 Pages) National Semiconductor (TI) – Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

DRAM Interface Timing Specification
**The CLK signal is only included as a reference; no specifications are guarantee to this signal.
FIGURE 8. DRAM Timing Diagram
TABLE 17. 4 Cycle Page Miss Preliminary Specifications
Symbol
t_ASC
t_ASR
t_CAC
t_CAH
t_CAS
t_CP
t_DH
t_DS
t_OFF
t_RAS
t_RAH
t_RCD
t_RCH
t_RCS
t_RP
t_WCH
t_WCS
Parameter
Column Address Setup Time
Row Address Setup Time
Access Time from CAS
Column Address Hold Time
CAS Pulse Width
Page Mode CAS Precharge
Write Data Hold Time
Write Data Setup Time
Read Data Valid Hold Time
RAS Pulse Width
Row Address Hold Time
RAS to CAS Delay Time
Read Command Hold Time
Read Command Setup Time
RAS Precharge Time
Write Command Hold Time
Write Command Setup Time
Formula
0.5T +
0.5T +
0.5T +
0.5T +
0.5T +
0.5T +
0.5T +
0.5T +
2.5T +
0.5T +
1.5T +
0.5T +
1.5T +
0.5T +
0.5T +
TABLE 18. 3 Cycle Miss Preliminary Specifications
Symbol
t_ASC
t_ASR
t_CAC
t_CAH
t_CAS
t_CP
t_DH
t_DS
Parameter
Column Address Setup Time
Row Address Setup time
Access Time from CAS
Column Address Hold Time
CAS Pulse Width
Page Mode CAS Precharge
Write Data Hold Time
Write Data Setup Time
Formula
0.5T +
0.5T +
0.5T +
0.5T +
0.5T +
0.5T +
0.5T +
0.5T +
19
DS100121-13
Min
Max
−20
−20
−5
−5
0
10
−10
−5
−20
0
−15 Progr’m’ble
−10
−20
0
−20
−10
−5
−20
Min
Max
−20
−20
−5
−5
0
10
−10
−5
−20
www.national.com