NS486SXL Datasheet, PDF (12/26 Pages) National Semiconductor (TI) – Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

2.0 SXL Pin Description Tables (Continued)
TABLE 11. Oscillator Pins (Continued)
Symbol
OSCX2
Pins
23
Type
O
Function
OSCillator Crystal 2 output. This is the output side of the NS486SXL on-chip
circuitry provided to support an external crystal circuit. If a TTL oscillator drives
OSCX1, this pin should be a no connect.
Symbol
Tx
Rx
UCLK
RTS
DSR
DTR
DCD
CTS
Pins
33
34
35
28
29
30
25
26
TABLE 12. 16550 UART Pins
Type
O
I
O
O
I
O
I
I
Function
UART Transmit data. In IrDA and HP-SIR mode this pin is the UART out-put
encoded for the serial infrared link. Otherwise it is the transmit output of the
16550 UART.
UART Receive data. In IrDA and HP-SIR mode this pin is routed through the
serial infrared decoder. Otherwise, it is the receive input to the 16550.
Uart CLocK. Output of programmable rate UART/MODEM clock. Typically used
for the Infrared Modulator.
Request To Send. When low, this signal informs the MODEM or data set that the
UART is ready to exchange data. The RTS output signal can be set to an active
low by programming bit 2 (RTS) of the MODEM Control Register. A Master Reset
operation sets this signal to its inactive (high) state. Loop mode operation holds
this signal in its inactive state.
Data Set Ready. When low, it indicates that the MODEM or data set is ready to
link with the UART. The DSR signal is a MODEM status input whose condition
can be tested by reading bit 5 (DSR) of the MODEM Status Register. Bit 5 is the
complement of the DSR signal. Bit 1 (DDSR) of the MODEM Status Register
indicates whether the DSR input has changed state since the previous reading of
the MODEM Status Register.
Note: Whenever the DSR bit of the MODEM Status Register changes state, an interrupt is generated
if the MODEM Status Interrupt is enabled.
Data Terminal Ready. When low, this signal informs the MODEM or data set that
the UART is ready to establish a communications link. The DTR output signal can
be set to an active low by programming bit 0 (DTR) of the MODEM Control
Register to a high level. A Master Reset operation sets this signal to its inactive
(high) state. Loop mode operation holds this signal in its inactive state.
Data Carrier Detect. When low, this input signal indicates that the data carrier has
been detected by the MODEM or data set. The DCD signal is a MODEM status
input whose condition can be tested by reading bit 7 (DCD) of the MODEM Status
Register. Bit 7 is the complement of the DCD signal. Bit 3 (DDCD) of the MODEM
Status Register indicates whether the DCD input has changed state since the
previous reading of the MODEM Status Register. DCD has no effect on the
receiver.
Note: Whenever the DCD bit of the MODEM Status Register changes state, an interrupt is generated
if the MODEM Status Interrupt is enabled
Clear To Send. When low, this input signal indicates that the MODEM or data set
is ready to exchange data. The CTS signal is a MODEM status input whose
conditions can be tested by reading bit 4 (CTS) of the MODEM Status Register.
Bit 4 is the complement of the CTS signal. Bit 0 (DCTS) of the MODEM Status
Register indicates whether the CTS input has changed state since the previous
reading of the MODEM Status Register. CTS has no effect on the Transmitter.
Note: Whenever the CTS bit of the MODEM Status Register changes state, an interrupt is generated
if the MODEM Status Interrupt is enabled.
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