NS486SXL Datasheet, PDF (5/26 Pages) National Semiconductor (TI) – Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

1.0 System Overview (Continued)
1.3.6 Power Management Features
The NS486SXL power management structure includes a
number of power saving mechanisms that can be combined
to achieve comprehensive power savings under a variety of
system conditions. First of all, the core processor power con-
sumption can be controlled by varying the processor/system
clock frequency. The internal CPU clock can be divided by 4,
8, 16, 32 or 64. In addition, in idle mode, the internal proces-
sor clock will be disabled. Finally, if an external crystal oscil-
lator circuit is being used, it can be disabled. For maximum
power savings, all internal clocks can be disabled (except for
the real-time clock oscillator).
The clocks of the on-board peripherals can be individually or
globally controlled. By setting bits in the power management
control registers, the internal clocks to the three-wire inter-
face, the timer, the DRAM controller, and the UART can be
disabled.
In addition to these internal clocks, the external SYSCLK can
be disabled via a bit in the power management control regis-
ters.
Using various combinations of these power saving controls
with the NS486SXL controller will result in excellent pro-
grammable power management for any application.
1.4 NS486SXL SYSTEM BUS
The NS486SXL system bus provides the interface to off-chip
peripherals and memory. It offers an ISA compatible inter-
face and is therefore capable of directly interfacing to many
ISA peripheral control devices. The interface is accom-
plished through the Bus Interface Unit (BIU). The BIU gener-
ates all of the access signals for both internal and external
peripherals and memory. Depending upon whether the ac-
cess is to internal peripherals, external peripherals or exter-
nal memory, the BIU generates the timing and control sig-
nals to access those resources. The BIU is designed to
support a glueless interface to many ISA-type peripherals.
For debug purposes, the NS486SXL can be set to generate
external bus cycles at the same time as an internal periph-
eral access takes place. This gives logic analyzers or other
debug tools the ability to track and capture internal periph-
eral accesses.
FIGURE 2. NS486SXL Internal Busses
DS100121-3
Access to internal peripherals is accomplished in three CPU
T-states (clock cycles). The fastest access to off-chip I/O is
also three T-states. When accessing off-chip memory and
I/O, wait state generation is accomplished through a combi-
nation of NS486SXL chip select logic and off-chip peripheral
feedback signals.
The ISA-like bus on the NS486SXL also supports External
Bus Masters. This feature allows external processors or I/O
Peripherals (and customer proprietary ASICs) with built-in
DMA controllers to read and write System DRAM supported
by the ’SXL DRAM Controller. External Masters can also ac-
cess any internal or external peripherals or memory as well.
The external master address must be at TRI-STATE^®
(through external address transceivers if necessary) in order
to support external master access to the DRAM.
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