NS486SXL Datasheet, PDF (20/26 Pages) National Semiconductor (TI) – Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

DRAM Interface Timing Specification (Continued)
TABLE 18. 3 Cycle Miss Preliminary Specifications (Continued)
Symbol
t_OFF
t_RAS
t_RAH
t_RCD
t_RCH
t_RCS
t_RP
t_WCH
t_WCS
Parameter
Read Data Valid Hold Time
RAS Pulse Width
Row Address Hold Time
RAS to CAS Delay Time
Read Command Hold Time
Read Command Setup Time
RAS Precharge Time
Write Command Hold Time
Write Command Setup Time
Formula
2.0T +
0.5T +
1.0T +
0.5T +
1.0T +
0.5T +
0.5T +
ISA-like Bus Cycles Timing
Specification
Min
Max
0
−15
PROG
−10
−20
0
−20
0
−5
−20
**The CLK signal is only included as a reference; no specifications are guarantee to this signal.
FIGURE 9. ISA-like Bus Timing Diagram
Symbol
t_AHCD
t_ASCD
t_CDPW
t_CHCD
t_CSCD
t_DOFF
t_RCAT
TABLE 19. No Command Delay ISA-like Bus Specifications
Parameter
Address Hold Time from CMD
Address Setup Time to CMD
Command Pulse Width
Chip Select Hold Time from CMD
Chip Select Setup Time to CMD
Read Data TRI-STATE
Read CMD Data Access Time
Formula
1.0T +
1.0T +
1.0T + (Wait)T +
1.0T +
1.0T +
1.0T +
1.0T + (Wait)T +
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DS100121-14
Min
Max
−20
−20
−10
−25
−40
−25
−30