DS90CR485 Datasheet, PDF (7/16 Pages) National Semiconductor (TI) – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

DS90CR485 Pin Description—Channel Link Serializer
Pin Name I/O
D0-D23
I
CLKIN
I
PD
I
TxOUTP
O
TxOUTM
O
CLK1P
O
CLK1M
O
PLLSEL
I
PRE
I
BAL
I
DS_OPT
I
TSEN
O
PRBS_EN I
PAT_SEL I
CON1
I
CON2
I
CON3
I
CON4
I
CON5 to
I
CON8
No. of
Pins
24
1
1
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
4
Description
LVCMOS/LVTTL level single-ended inputs. 3V tolerant when V_CC3V = 3.3V.
Note, external pull-down resistor of 1kΩ is required on all unused input data pins.
LVCMOS/LVTTL level clock input. Samples data on both edges. See Figure 5 and Figure 9.
3V tolerant when V_CC3V = 3.3V.
LVCMOS/LVTTL level input. PD = low activates the powerdown function and minimizes power
dissipation. 3V tolerant when V_CC3V = 3.3V. (Note 9)
Positive LVDS differential data output.
Negative LVDS differential data output.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
LVCMOS/LVTTL level single-ended inputs. Control input for PLL range select. This pin must be
tied to V_CC for 66MHz to 133 MHz operation. No connect or tied to low is reserved for future use.
3V tolerant when V_CC3V = 3.3V. (Note 9)
LVCMOS/LVTTL level single-ended inputs. Pre-emphasis level select. Pre-emphasis is active
when input is tied to V_CC through external pull-up resistor. Resistor value determines
pre-emphasis level (see table in application section). For normal LVDS levels (no pre-emphasis),
leave this pin open (do not tie to ground).
3V tolerant when V_CC3V = 3.3V.
LVCMOS/LVTTL level single-ended inputs. TTL level input. Tied this pin to Vcc to enable DC
Balance function. When tied low or left open, the DC Balance function is disabled. Please refer to
the Applications Information on the back for more information. See Figure 9 and Figure 10.
3V tolerant when V_CC3V = 3.3V.
LVCMOS/LVTTL level single-ended inputs. Cable Deskew performed when TTL level input is low.
No TxIN data is sampled during Deskew. To perform Deskew function, input must be held low for
a minimum of 4096 clock cycles. The Deskew operation is normally conducted after the TX and
RX PLLs have locked. It should also be conducted after a system reset, or a reconfiguration
event. Please refer to Applications Information section in back of this datasheet for more
information.
3V tolerant when V_CC3V = 3.3V.
Termination Sense pin. The logic state output of this pin reports the presence of a remote
termination resistor. TSEN is LOW when NO termination has been detected. TSEN is HIGH when
a termination of 100Ω has been detected.
Note, TSEN pin is an open-collector output, an external pull-up resistor of 1kΩ is required in order
for TSEN pin to function.
PRBS generator enable pin. The Pseudo Random Binary Sequence (PRBS) generator is enable
when this pin is tied High. Tie Low or float to disable the PRBS generator.
3V tolerant when V_CC3V = 3.3V.
PRBS-23 or PRBS-15 mode selection pin. PRBS-23 mode is enabled when this pin is tied High.
Tie Low or float to enable PRBS-15 mode.
3V tolerant when V_CC3V = 3.3V.
Control pin. This pin is reserved for future use. Tied to Low or NC.
Control pin. This pin must be tied High or pulled to high for normal operation Tied to Low for
internal BIST function only. Do not float.
3V tolerant when V_CC3V = 3.3V.
Control pin. This pin must be tied Low to configure the device for specific operation. Tied to
High or floating is reserved for future use.
Control pin. When tied High, all eight LVDS output channels (A0-A7) are enabled. Tied to Low will
disable LVDS output channels A4-A7. Must tie High for standard operation.
3V tolerant when V_CC3V = 3.3V.
Control pins. Tied to Low for normal operation.
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