DS90CR485 Datasheet, PDF (3/16 Pages) National Semiconductor (TI) – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

Recommended Input Requirements
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
Symbol
Parameter
Min Typ Max Units
TCIP TxCLK IN Period (Figure 4)
7.52
T 15.15 ns
TCIH TxCLK in High Time (Figure 4)
0.35T 0.5T 0.65T ns
TCIL TxCLK in Low Time (Figure 4)
0.35T 0.5T 0.65T ns
TCIT TxCLK IN Transition Time (Figure 3)
66MHz
0.5
2.4 ns
133MHz
0.5
1.2 ns
TXIT D0 to D23 Transition Time
66MHz
0.5
2.9 ns
133MHz
0.5
1.75 ns
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
Symbol
Parameter
Min
LLHT
LVDS Low-to-High Transition Time (No pre-emphasis, PRE = open) (Figure 2)
(Note 3)
LVDS Low-to-High Transition Time (max. pre-emphasis, PRE = V_CC) (Figure 2)
(Note 3)
LHLT
LVDS High-to-Low Transition Time (No pre-emphasis, PRE = open) (Figure 2)
(Note 3)
LVDS High-to-Low Transition Time (max. pre-emphasis, PRE = V_CC) (Figure 2)
(Note 3)
TCCS TxOUT Channel-to-Channel Skew
TPPOS Transmitter Output Pulse Position. (Note 4)
f = 133 MHz
−100
f = 100 MHz
−150
f = 66 MHz
−200
TSTC TxIN Setup to CLKIN at 133 MHz (Note 5), (Figure 5)
0.5
THTC CLKIN to TxIN Hold at 133 MHz (Note 5), (Figure 5)
0.5
TJCC Transmitter Jitter Cycle-to-Cycle (Note 6)
f = 133 MHz
f = 100 MHz
f = 66 MHz
BWPLL PLL Bandwidth ≥ 66MHz
TPLLS Transmitter Phase Lock Loop Set (Figure 6)
TPDD Transmitter Powerdown Delay (Figure 7)
TPDL Transmitter Input to Output Latency (Figure 8)
6(TCIP)
Typ
0.2
0.12
0.19
0.1
20
40
45
50
600
7(TCIP)
Max
0.4
0.2
0.4
0.2
+100
+150
+ 200
70
80
100
10
100
8(TCIP)
Units
ns
ns
ns
ns
ps
ps
ps
ps
ns
ns
ps
ps
ps
kHz
ms
ns
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 2.5V and T_A = +25˚C.
Note 3: LLHT and LHLT are measurements of transmitter LVDS data outputs rise and fall time over the recommended frequency range. The limits are based on
bench characterization and Guaranteed By Design (GBD) using statistical analysis.
Note 4: TPPOS is a measure of transmitter output pulse position in comparison with the ideal pulse position over the recommended frequency range. The limits are
based on bench characterization and Guaranteed By Design (GBD) using statistical analysis.
Note 5: TSTC and THTC are measurements of transmitter data inputs setup and hold time with clock input, CLKIN. The limits are based on bench characterization
and Guaranteed By Design (GBD) using statistical analysis.
Note 6: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a
cycle-to-cycle jitter of ±10% at a 1µs rate applied to the transmitter’s input clock signal (CLKIN) while data inputs are switching with internal PRBS generator enabled
without DC-Balance. The typical data is measured with a cycle-to-cycle jitter of ±100ps applied to the transmitter’s input clock signal (CLKIN).
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