DS90CR485 Datasheet, PDF (1/16 Pages) National Semiconductor (TI) – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

September 2003
DS90CR485
133MHz 48-bit Channel Link Serializer (6.384 Gbps)
General Description
The DS90CR485 serializes the 24 LVCMOS/LVTTL double
edge inputs (48 bits data latched in per clock cycle) onto 8
Low Voltage Differential Signaling (LVDS) streams. A phase-
locked transmit clock is also in parallel with the data streams
over a 9th LVDS link. The reduction of the wide TTL bus to a
few LVDS lines reduces cable and connector size and cost.
The double edge input strobes data on both the rising and
falling edges of the clock. This minimizes the pin count
required and simplifies PCB routing between the host chip
and the serializer.
This chip is an ideal solution to solve EMI and interconnect
size problems for high throughput point-to-point applications.
The DS90CR485 is intended for use with the DS90CR486
Channel-Link receiver. It is also backward compatible with
other Channel-Link receiver such as the DS90CR482 and
DS90CR484.
For more details, please refer to the “Applications Informa-
tion” section of this datasheet.
Features
n Up to 6.384 Gbps throughput
n 66MHz to 133MHz input clock support
n Reduces cable and connector size and cost
n Pre-emphasis reduces cable loading effects
n DC balance reduces ISI distortion
n 24 bit double edge inputs
n 3V Tolerant LVCMOS/LVTTL inputs
n Low power, 2.5V supply
n Flow-through pinout
n In 100-pin TQFP package
n Conforms with TIA/EIA-644-A LVDS standard.
Generalized Block Diagram
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