DS90CR485 Datasheet, PDF (4/16 Pages) National Semiconductor (TI) – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern (Note 7)
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVCMOS/LVTTL I/O.
20019532
FIGURE 2. LVDS Output Load and Transition Times
20019512
20019514
FIGURE 3. Input Clock Transition Time
FIGURE 4. Input Clock High/Low Times
20019554
www.national.com
4