DS90CR485 Datasheet, PDF (12/16 Pages) National Semiconductor (TI) – 133MHz 48-bit Channel Link Serializer (6.384 Gbps)

Applications Information (Continued)
POWER-UP SEQUENCE AND 3V TOLERANT
The DS90CR485 inputs provide an option for 3.3V tolerant.
If this is required, the V_CC3V pin must be connected to a 3.3V
rail. Also when power is applied to the transmitter, V_CC3V pin
must be applied before or simultaneously with other power
supply pins (2.5V). If 3.3V tolerance is not required, this pin
may be tied to the 2.5V rail.
LVDS OUTPUT
This device features a modified LVDS output that provides
an internal, 100Ω termination at the source side of the link to
control of reflections. An external termination resistor is re-
quired at the far end of the link and should be placed as
close to the receiver inputs as possible to minimize any
resulting stub length. Unused LVDS output channels should
be terminated with 100Ω at the transmitter’s output pin.
POWER DOWN
When the Power Down feature is asserted (PD = Low), the
current draw through the supply pins is minimized and the
PLL is shut down. The transmitter outputs are in TRI-STATE
when in power down mode. The PD pin should be driven
HIGH to enable the device once V_CC is stable.
DESKEW
The receiver will deskew or compensate the fixed intercon-
nect skew between data signals, with respect to the rising
edge of clock, on each of the independent differential pairs
(pair-to-pair skew). For a list of deskew ranges, please refer
to the corresponding receiver datasheet for more informa-
tion.
In order for the deskew function to work properly, it must be
initialized or calibrated. The DS90CR486 deskew can be
initialized with any data pattern with a transition over a period
of three clock cycles. Therefore, there are multiple ways to
initialize the deskew function depending on the setup con-
figuration. For example, to initialize the operation of deskew
for DS90CR485 and DS90CR486 in DC balance mode, the
DS_OPT pin at the input of the transmitter DS90CR485 can
be set High OR Low when power up. The period of this input
to the DS_OPT pin must be at least 20ms (TX and RX PLLs
lock time) plus 4096 clock cycles in order for the receiver to
complete the deskew operation. For other configuration
setup with DS90CR483 and DS90CR484, please refer to the
flow chart on Figure 11.
The DS_OPT pin at the input of the transmitter
(DS90CR485) is used to initiate the deskew calibration pat-
tern. Depends on the configuration, it can be set High or Low
when power up in order for the receiver to complete the
deskew operation. For this reason, the LVDS clock signal
with DS_OPT applied high (active data sampling) shall be
1111000 or 1110000 pattern and the LVDS data lines (Tx-
OUT 0-7) shall be High for one clock cycle and Low for the
next clock cycle. During the deskew operation with DS_OPT
applied low, the LVDS clock signal shall be 1111100 or
1100000 pattern. The transmitter will also output a series of
1111000 or 1110000 onto the LVDS data lines (TxOUT 0-7)
during deskew so that the receiver can automatically cali-
brated the data sampling strobes at the receiver inputs. Each
data channel is deskewed independently and is tuned over a
specific range. Please refer to corresponding receiver
datasheet for a list of deskew ranges.
Note that the deskew initialization must be performed at
least once after the PLL has locked to the input clock fre-
quency, and it must be done at the time when the receiver is
powered up and PLL has locked. If power is lost, or if the
cable has been switched or disconnected, the initialization
procedure must be repeated or else the receiver may not
sample the incoming LVDS data correctly.
HOW TO CONFIGURE FOR BACKPLANE
APPLICATIONS
In a backplane application with differential line impedance of
100Ω the differential line pair-to-pair skew can controlled by
trace layout. In a backplane application with short PCB
distance traces, pre-emphasis from the transmitter is typi-
cally not required. The "PRE" pin should be left open (do not
tie to ground). A resistor pad provision for a pull up resistor to
V_CC can be implemented in case pre-emphasis is needed to
counteract heavy capacitive loading effects.
HOW TO CONFIGURE FOR CABLE INTERCONNECT
APPLICATIONS
In applications that require the long cable drive capability,
the DS90CR485 offers higher bandwidth support and longer
cable drive with the use of DC balanced data transmission,
pre-emphasis. Cable drive is enhanced with a user select-
able pre-emphasis feature that provides additional output
current during transitions to counteract cable loading effects.
This requires the use of one pull-up resistor to V_CC; please
refer to Table 1 to set the level needed. Optional DC balanc-
ing on a cycle-to-cycle basis, is also provided to reduce ISI
(Inter-Symbol Interference) for long cable applications. With
pre-emphasis and DC balancing, a low distortion eye-pattern
is provided at the receiver end of the cable.
SUPPLY BYPASS RECOMMENDATIONS
Bypass capacitors must be used on the power supply pins.
Different pins supply different portions of the circuit, there-
fore capacitors should be nearby all power supply pins ex-
cept as noted in the pin description table. Use high fre-
quency ceramic (surface mount recommended) 0.1µF
capacitors close to each supply pin. If space allows, a
0.01µF capacitor should be used in parallel, with the small-
est value closest to the device pin. Additional scattered
capacitors over the printed circuit board will improve decou-
pling. Multiple (large) via should be used to connect the
decoupling capacitors to the power plane. A 4.7 to 10µF bulk
cap is recommended near the PLLVCC pins and also the
LVDSVCC pins. Connections between the caps and the pin
should use wide traces.
INPUT SIGNAL QUALITY REQUIREMENT
The input signal quality must comply to the datasheet re-
quirements, please refer to the "Recommended Transmitter
Input Characteristics" table for specifications. In addition
undershoots in excess of the ABS MAX specifications are
not recommended. If the line between the host device and
the transmitter is long and acts as a transmission line, then
termination should be employed. If the transmitter is being
driven from a device with programmable drive strength, data
inputs are recommended to be set to a weak setting to
prevent transmission line effects. The clock signal is typically
set higher to provide a clean edge that is also low jitter.
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
jUse 100Ω coupled differential pairs
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