COP224C Datasheet, PDF (7/24 Pages) National Semiconductor (TI) – Single-Chip 1k and 2k CMOS Microcontrollers

Functional Description (Continued)
overflow flag will be set (see SKT and IT instructions below)
The T counter is cleared on reset A functional block dia-
gram of the timer counter is illustrated in Figure 7
Four general-purpose inputs IN3–IN0 are provided
The D register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of Bd
The G register contents are outputs to a 4-bit general-pur-
pose bidirectional I O port
The Q register is an internal latched 8-bit register used to
hold data loaded to or from M and A as well as 8-bit data
from ROM Its contents are outputted to the L I O ports
when the L drivers are enabled under program control
The 8 L drivers when enabled output the contents of
latched Q data to the L I O port Also the contents of L may
be read directly into A and M
The SIO register functions as a 4-bit serial-in serial-out shift
register for MICROWIRE I O and COPS peripherals or as a
binary counter (depending on the contents of the EN regis-
ter) Its contents can be exchanged with A
The XAS instruction copies C into the SKL latch In the
counter mode SK is the output of SKL in the shift register
mode SK outputs SKL ANDed with the clock
EN is an internal 4-bit register loaded by the LEI instruction
The state of each bit of this register selects or deselects the
particular feature associated with each bit of the EN regis-
ter
0 The least significant bit of the enable register EN0 se-
lects the SIO register as either a 4-bit shift register or a
4-bit binary counter With EN0 set SIO is an asynchro-
nous binary counter decrementing its value by one upon
each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI
input Each pulse must be at least two instruction cycles
wide SK outputs the value of SKL The SO output equals
the value of EN3 With EN0 reset SIO is a serial shift
register left shifting 1 bit each instruction cycle time The
data present at SI goes into the least significant bit of
SIO SO can be enabled to output the most significant bit
of SIO each cycle time The SK outputs SKL ANDed with
the instruction cycle clock
1 With EN1 set interrupt is enabled Immediately following
an interrupt EN1 is reset to disable further interrupts
2 With EN2 set the L drivers are enabled to output the data
in Q to the L I O port Resetting EN2 disables the L driv-
ers placing the L I O port in a high-impedance input
state
3 EN3 in conjunction with EN0 affects the SO output With
EN0 set (binary counter option selected) SO will output
the value loaded into EN3 With EN0 reset (serial shift
register option selected) setting EN3 enables SO as the
output of the SIO shift register outputting serial shifted
data each instruction time Resetting EN3 with the serial
shift register option selected disables SO as the shift reg-
ister output data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains set to ‘‘0’’
INTERRUPT
The following features are associated with interrupt proce-
dure and protocol and must be considered by the program-
mer when utilizing interrupts
a The interrupt once recognized as explained below
pushes the next sequential program counter address
(PCa1) onto the stack Any previous contents at the bot-
tom of the stack are lost The program counter is set to
hex address 0FF (the last word of page 3) and EN1 is
reset
b An interrupt will be recognized only on the following con-
ditions
1 EN1 has been set
2 A low-going pulse (‘‘1’’ to ‘‘0’’) at least two instruction
cycles wide has occurred on the IN₁ input
3 A currently executing instruction has been completed
FIGURE 3 Input Output Timing Diagrams (divide by 8 mode)
TABLE I Enable Register Modes Bits EN0 and EN3
EN0 EN3 SIO
SI
SO
SK
0 0 Shift
Input to Shift 0 If SKLe1 SKeclock
Register Register
If SKLe0 SKe0
0 1 Shift
Input to Shift Serial If SKLe1 SKeclock
Register Register out If SKLe0 SKe0
1 0 Binary Input to
0 SKeSKL
Counter Counter
1 1 Binary Input to
1 SKeSKL
Counter Counter
7
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