COP224C Datasheet, PDF (14/24 Pages) National Semiconductor (TI) – Single-Chip 1k and 2k CMOS Microcontrollers

Instruction Set (Continued)
TABLE III COP244C 245C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language
Code
(Binary)
Data Flow
Skip
Conditions
INPUT OUTPUT INSTRUCTIONS
ING
33
0011 0011
GxA
None
2A
0010 1010
Description
Input G Ports to A
ININ
33
0011 0011
INxA
None
Input IN Inputs to A
28
0010 1000
(Note 2)
INIL
33
0011 0011
x IL₃ CKO ‘‘0’’ IL₀ A None
Input IL Latches to A
29
0010 1001
(Note 3)
INL
OBD
33
0011 0011
x L_{7 4} RAM(B)
2E
0010 1110
x L_{3 0} A
33
0011 0011
BdxD
3E
0011 1110
None
None
Input L Ports to RAM A
Output Bd to D Outputs
OGI
y
33
0011 0011
yxG
5b
0101 y
None
Output to G Ports
Immediate
OMG
33
0011 0011
RAM(B)xG
3A
0011 1010
None
Output RAM to G Ports
XAS
4F
0100 1111
A
SIO CxSKL
None
Exchange A with SIO
(Note 3)
Note 1 All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e g Br and Bd are explicitly defined) Bits are numbered 0 to N where
0 signifies the least significant bit (low-order right-most bit) For example A₃ indicates the most significant (left-most) bit of the 4-bit A register
Note 2 The ININ instruction is not available on the 24-pin packages since these devices do not contain the IN inputs
Note 3 For additional information on the operation of the XAS JID LQID INIL and SKT instructions see below
Note 4 The JP instruction allows a jump while in subroutine pages 2 or 3 to any ROM location within the two-page boundary of pages 2 or 3 The JP instruction
otherwise permits a jump to a ROM location within the current 64-word page JP may not jump to the last word of a page
Note 5 A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P) A JSRP may not be used when in pages 2 or 3 JSRP
may not jump to the last word in page 2
Note 6 LBI is a single-byte instruction if d e 0 9 10 11 12 13 14 or 15 The machine code for the lower 4 bits equals the binary value of the ‘‘d’’ data minus 1
e g to load the lower four bits of B(Bd) with the value 9 (1001₂) the lower 4 bits of the LBI instruction equal 8 (1000₂) To load 0 the lower 4 bits of the LBI
instruction should equal 15 (1111₂)
Note 7 Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN where a ‘‘1’’ or ‘‘0’’ in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit (See Functional Description EN Register )
Note 8 For 2K ROM devices A
x Br (0 A3) For 1K ROM devices A
x Br (0 0 A3 A2)
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