COP224C Datasheet, PDF (13/24 Pages) National Semiconductor (TI) – Single-Chip 1k and 2k CMOS Microcontrollers

Instruction Set (Continued)
TABLE III COP244C 245C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language
Code
(Binary)
Data Flow
Skip
Conditions
MEMORY REFERENCE INSTRUCTIONS (Continued)
STII
y
7b
0111 y
yxRAM(B)
None
Bd a 1xBd
X
r
b6
00 r 0110
RAM(B)
A
None
(re0 3)
x Br Z r Br
XAD
rd
23
0010 0011
RAM(r d)
A None
bb
1r d
XDS
r
b7
00 r 0111
RAM(B)
A Bd
(re0 3)
Bdb1xBd
decrements
x Br Z r Br
past 0
XIS
r
b4
00 r 0100
(re0 3)
REGISTER REFERENCE INSTRUCTIONS
CAB
50
0101 0000
RAM(B)
A
Bda1xBd
x Br Z r Br
AxBd
Bd
increments
past 15
None
CBA
4E
0100 1110
BdxA
None
LBI
rd
bb
00 r (d– 1)
r dxB
Skip until
(re0 3
not a LBI
de0 9 15)
or
33
0011 0011
bb
1r d
(any r any d)
LEI
y
33
0011 0011
yxEN
None
6b
0110 y
XABR
12
0001 0010
A
Br
None
TEST INSTRUCTIONS
SKC
20
0010 0000
Ce‘‘1’’
SKE
21
0010 0001
AeRAM(B)
SKGZ
33
0011 0011
21
0010 0001
G_{3 0}e0
SKGBZ
SKMBZ
SKT
33
0011 0011
1st byte
0
01
0000 0001
1
11
0001 0001
2
3
03
13
* ^{0000 0011}
0001 0011
2nd byte
0
01
0000 0001
1
11
0001 0001
2
03
0000 0011
3
13
0001 0011
41
0100 0001
G₀e0
G₁e0
G₂e0
G₃e0
RAM(B)₀e0
RAM(B)₁e0
RAM(B)₂e0
RAM(B)₃e0
A time-base
counter carry
has occurred
since last test
Description
Store Memory Immediate
1 and Increment Bd
Exchange RAM with A
Exclusive-OR Br with r
Exchange A with RAM
Pointed to Directly by r d
Exchange RAM with A
and Decrement Bd
Exclusive-OR Br with r
Exchange RAM with A
and Increment Bd
Exclusive-OR Br with r
Copy A to Bd
Copy Bd to A
Load B Immediate with r d
(Note 6)
Load EN Immediate (Note 7)
Exchange A with Br (Note 8)
Skip if C is True
Skip if A Equals RAM
Skip if G is Zero
(all 4 bits)
Skip if G Bit is Zero
Skip if RAM Bit is Zero
Skip on Timer
(Note 3)
13