COP224C Datasheet, PDF (6/24 Pages) National Semiconductor (TI) – Single-Chip 1k and 2k CMOS Microcontrollers

Pin Descriptions
Pin
L7 – L0
G3 – G0
D3 – D0
IN3 – IN0
SI
SO
Description
8-bit bidirectional
port with TRI-STATE
4-bit bidirectional
I O port
4-bit output port
4-bit input port
(28 pin package only)
Serial input or
counter input
Serial or general
purpose output
Functional Description
The internal architecture is shown in Figure 1 Data paths
are illustrated in simplified form to depict how the various
logic elements communicate with each other in implement-
ing the instruction set of the device Positive logic is used
When a bit is set it is a logic ‘‘1’’ when a bit is reset it is a
logic ‘‘0’’
Caution
The output options available on the COP224C 225C 226C
and COP244C 245C are not the same as those available
on the COP324C 325C 326C COP344C 345C COP424C
425C 426C and COP444C 445C Options not available on
the COP224C 225C 226C and COP244C 245C are Option
2 value 2 Option 4 value 0 Option 5 value 1 Option 9 value
0 Option 17 value 1 Option 30 Dual Clock all values Op-
tion 32 Microbus^TM all values Option 33 values 2 4 and 6
Option 34 all values and Option 35 all values
PROGRAM MEMORY
Program Memory consists of ROM 1024 bytes for the
COP224C 225C 226C and 2048 bytes for the COP244C
245C These bytes of ROM may be program instructions
constants or ROM addressing data
ROM addressing is accomplished by an 11-bit PC register
which selects one of the 8-bit words contained in ROM A
new address is loaded into the PC register during each in-
struction cycle Unless the instruction is a transfer of control
instruction the PC register is loaded with the next sequen-
tial 11-bit binary count value
Three levels of subroutine nesting are implemented by a
three level deep stack Each subroutine call or interrupt
pushes the next PC address into the stack Each return
pops the stack back into the PC register
DATA MEMORY
Data memory consists of a 512-bit RAM for the COP244C
245C organized as 8 data registers of 16 c 4-bit digits
Pin
SK
CKI
CKO
RESET
V_CC
GND
Description
Logic controlled
clock output
Chip oscillator input
Oscillator output
HALT I O port or
general purpose input
Reset input
Most positive
power supply
Ground
RAM addressing is implemented by a 7-bit B register whose
upper 3 bits (Br) select 1 of 8 data registers and lower 4 bits
(Bd) select 1 of 16 4-bit digits in the selected data register
Data memory consists of a 256-bit RAM for the COP224C
225C 226C organized as 4 data registers of 16 c 4-bits
digits The B register is 6 bits long Upper 2 bits (Br) select 1
of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit
digits in the selected data register While the 4-bit contents
of the selected RAM digit (M) are usually loaded into or
from or exchanged with the A register (accumulator) it
may also be loaded into or from the Q latches or T counter
or loaded from the L ports RAM addressing may also be
performed directly by the LDD and XAD instructions based
upon the immediate operand field of these instructions
The Bd register also serves as a source register for 4-bit
data sent directly to the D outputs
INTERNAL LOGIC
The processor contains its own 4-bit A register (accumula-
tor) which is the source and destination register for most I O
arithmetic logic and data memory access operations It can
also be used to load the Br and Bd portions of the B regis-
ter to load and input 4 bits of the 8-bit Q latch or T counter
to input 4 bits of L I O ports data to input 4-bit G or IN
ports and to perform data exchanges with the SIO register
A 4-bit adder performs the arithmetic and logic functions
storing the results in A It also outputs a carry bit to the 1-bit
C register most often employed to indicate arithmetic over-
flow The C register in conjunction with the XAS instruction
and the EN register also serves to control the SK output
The 8-bit T counter is a binary up counter which can be
loaded to and from M and A using CAMT and CTMA instruc-
tions This counter may be operated in two modes depend-
ing on a mask-programmable option as a timer or as an
external event counter When the T counter overflows an
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