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LMH0031 Datasheet, PDF (6/31 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Deserializer Descrambler with Video and Ancillary Data FIFOs
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Required Input Conditions (Continued)
Symbol
fACLK
DCACLK
tr, tf
tS
tH
RREF
fEXT CLK
fXTAL
Parameter
Conditions
Ancillary / Control Data
Clock Frequency
Duty Cycle, Ancillary Clock
Ancillary / Control Clock
and Data Rise Time, Fall 10%–90%
Time
Setup Time, ADN to ACLK
or ION to ACLK Rising
Edge
Control Data Input or
Hold Time, Rising Edge I/O Bus Input
ACLK to ADN or ACLK to
ION
Bias Supply Reference
Resistor
Tolerance 1%
External Clock Frequency
Crystal Frequency
Figure 6
Reference
Min
Typ
ACLK
45
50
1.0
1.5
3.0
1.5
ION, ADN, ACLK
Timing Diagram
3.0
1.5
Ext Clk
XTALo, XTALi
−100
ppm
4.75k
27.0
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).
Symbol
Parameter
Conditions
Reference
Min
Typ
VIH
VIL
IIH
IIL
VOH
VOL
VOHV
Input Voltage High Level
Input Voltage Low Level
Input Current High Level
Input Current Low Level
Output Voltage High Level
VIH = VDDIO(Note 8)
VIL = VSSIO
IOH = −2 mA
Output Voltage Low Level IOL = +2 mA
Minimum Dynamic VOH
IOH = −2 mA
(Note 6)
All LVCMOS
Inputs
All LVCMOS
Outputs
2.0
VSSIO
2.4
VSSIO
+85
−1
2.7
VSSIO
+0.3
VDDIO
−0.5
VOLP
Maximum Dynamic VOL
IOL = +2 mA
(Note 6)
VSSIO
+0.4
VSDI
ISDI
VTH
IBB
Serial Data Input Voltage
Serial Data Input Current
Input Thereshold
Bias Supply Output
Current
Over VCM range
RBB = 8.66kΩ 1%
SDI, SDI
125
−220
800
±1
<100
−188
IREF
Reference Output Current
Power Supply Current,
IDD (3.3V) 3.3V Supply, Total
Power Supply Current,
IDD (2.5V) 2.5V Supply, Total
RREF = 4.75kΩ 1%
270MBPS Data Rate
1,485MBPS Data Rate
270MBPS Data Rate
1,485MBPS Data Rate
VDDIO, VDDSI
VDDD, VDDPLL
−290
−262
38.0
47.0
80
220
Max
VCLK
55
3.0
+100
ppm
Max
VDDIO
0.8
+150
−20
VDDIO
VSSIO
+0.5V
880
±10
45.0
50.0
120
340
Units
MHz
%
ns
ns
ns
Ω
MHz
Units
V
µA
V
mVP-P
µA
mV
µA
mA
mA
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