LMH0031 Datasheet, PDF(22/31 Page) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Deserializer Descrambler with Video and Ancillary Data FIFOs

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LMH0031 Datasheet, PDF (22/31 Pages) National Semiconductor (TI) – SMPTE 292M/259M Digital Video Deserializer Descrambler with Video and Ancillary Data FIFOs

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Device Operation (Continued)

Format

Code

[4,3,2,1,0]

00001

00010

00011

01001

01010

01011

10001

10010

10011

11001

11010

11100

11101

10100

Format

SDTV, 54

SDTV, 36

SDTV, 27

SDTV, 54

SDTV, 36

SDTV, 27

HDTV, 74.25

TABLE 4. Video Raster Format Parameters

Spec.

RP 174

SMPTE 267

SMPTE 125

ITU-R BT 601.5

SMPTE 260

SMPTE 274

SMPTE 295

SMPTE 274

SMPTE 296 (1, 2)

Frame

Rate

60I

50I

30I

30P

25I

25P

25I

24P

60P

Lines

525

625

1125

1250

1125

750

Active Lines

507/487*

577

1035

1080

720

Samples

3432

2288

1716

3456

2304

1728

2200

2640

2376

2750

1650

Active

Samples

2880

1920

1440

2880

1920

1440

1920

1280

The HD Only bit when set to a logic-1 locks the LMH0031

into the high definition data range and frequency. In systems

designed to handle only high definition signals, enabling HD

Only reduces the time required for the LMH0031 to establish

frequency lock and determine the HD format being pro-

cessed.

The SD Only bit when set to a logic-1 locks the LMH0031

into the standard definition data ranges and frequencies. In

systems designed to handle only standard definition signals,

enabling SD Only reduces the time required for the

LMH0031 to establish frequency lock and determine the

format being processed. When SD Only and HD Only are

set to logic-0, the device operates in SD/HD mode.

The Framing Mode bit in the Format 0 register and Fram-

ing Enable in the Video Info 0 register combine with Fram-

ing Enable to control the manner in which the LMH0031

aligns framing. When Framing Mode and Framing Enable

are both reset, the LMH0031 aligns on the first valid TRS

character. If another TRS occurs that is not on a word

boundary, the NSP bit is set until the next TRS that is on a

word boundary occurs. When Framing Mode is set to a

logic-1, the LMH0031 operates similarly to the CLC011 when

NSP is tied to FE. An alternative configuration that operates

identically can be achieved with the LMH0031 by mapping

NSP as an output and Framing Enable as an input on the

Multifunction I/O bus and externally connecting them. In this

case Framing Mode should be reset to a logic-0. When

Framing Mode is reset and Framing Enable is set, the

LMH0031 realigns on every valid TRS. The initial state of

Framing Mode is set following a reset or at power-on.

FORMAT 1 (Address 0Ch)

The LMH0031 automatically determines the format of the

incoming serial data. The result of this operation is stored in

the FORMAT 1 register. The Format[4:0] bits identify which

of the many possible video data standards that the LMH0031

can process is being received. These format codes follow

the same arrangement as for the Format Set[4:0] bits.

These formats and codes are given in Table 4. Bit Format[4]

when set indicates that HD data is being processed. When

reset, SD data is indicated. Format[3] when set indicates

that PAL data is being processed. When reset NTSC data is

being processed. Format[2:0] correspond with one of the

sub-standards given in the table. Note that the LMH0031

does not distinguish or log the data rate differences between

HD data at 74.25Mhz and 74.25MHz/1.001.

The H, V, and F bits correspond to input TRS data bits 6, 7

and 8, respectively. The meaning and function of this data is

the same for both standard definition (SMPTE 125M) and

high definition (SMPTE 292M luminance and colour differ-

ence) video data. Polarity is logic-1 equals HIGH-true. These

bits are registered for the duration of the applicable field.

TEST 0 REGISTER (Address 0Dh)

The Test Pattern Select bits determine which test pattern is

output when the Test Pattern Generator (TPG) mode or the

Built-in Self-Test (BIST) mode is enabled. Table 5 gives the

codes corresponding to the various test patterns. All HD

colour bar test patterns are inherently BIST data. BIST test

patterns for SD are: NTSC, 27MHz, 4x3 Colour Bars and

PAL, 27MHz, 4x3 PLL Pathological.

The TPG Enable bit when set to a logic-1 enables the Test

Pattern Generator function and built-in self-test (BIST).

The Pass/Fail bit indicates the result of the built-in self-test.

This bit is a logic-1 for a pass condition.

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