DS90CR285 Datasheet, PDF (6/17 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

Receiver Switching Characteristics (Continued)
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
Parameter
Min
RSRC
RxOUT Setup to RxCLK OUT (Figure 7)
f = 40 MHz
6.5
f = 66 MHz
2.5
RHRC
RxOUT Hold to RxCLK OUT (Figure 7)
f = 40 MHz
6.0
f = 66 MHz
2.5
RCCD
RxCLK IN to RxCLK OUT Delay (Figure 9)
f = 40 MHz
4.0
f = 66 MHz
5.0
RPLLS
Receiver Phase Lock Loop Set (Figure 11)
RPDD
Receiver Powerdown Delay (Figure 15)
Typ Max Units
14.0
ns
8.0
ns
8.0
ns
4.0
ns
6.7
8.0
ns
6.6
9.0
ns
10
ms
1
µs
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference (both
dependent on type/length of cable), and clock jitter less than 250 ps).
Note 6: The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.
Note 7: The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
01291003
01291002
01291004
FIGURE 2. DS90CR285 (Transmitter) LVDS Output Load and Transition Times
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