DS90CR285 Datasheet, PDF (5/17 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

Transmitter Switching Characteristics (Continued)
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
Parameter
Min
Typ
TPPos3 Transmitter Output Pulse Position for Bit3
10.2
10.4
TPPos4 Transmitter Output Pulse Position for Bit4
13.7
13.9
TPPos5 Transmitter Output Pulse Position for Bit5
17.3
17.6
TPPos6 Transmitter Output Pulse Position for Bit6
21.0
21.2
TPPos0 Transmitter Output Pulse Position for Bit0 f = 66 MHz
−0.4
0
(Note 6) (Figure 16)
TPPos1 Transmitter Output Pulse Position for Bit1
1.8
2.2
TPPos2 Transmitter Output Pulse Position for Bit2
4.0
4.4
TPPos3 Transmitter Output Pulse Position for Bit3
6.2
6.6
TPPos4 Transmitter Output Pulse Position for Bit4
8.4
8.8
TPPos5 Transmitter Output Pulse Position for Bit5
10.6
11.0
TPPos6 Transmitter Output Pulse Position for Bit6
12.8
13.2
TCIP
TxCLK IN Period (Figure 6 )
15
T
TCIH
TxCLK IN High Time (Figure 6)
0.35T
0.5T
TCIL
TxCLK IN Low Time (Figure 6)
0.35T
0.5T
TSTC
TxIN Setup to TxCLK IN (Figure 6)
2.5
THTC
TxIN Hold to TxCLK IN (Figure 6)
0
TCCD
TxCLK IN to TxCLK OUT Delay @ 25˚C,V_CC=3.3V (Figure
3
3.7
8)
TPLLS
Transmitter Phase Lock Loop Set (Figure 10)
TPDD
Transmitter Powerdown Delay (Figure 14)
Max
11.0
14.6
18.2
21.8
0.3
2.5
4.7
6.9
9.1
11.3
13.5
50
0.65T
0.65T
5.5
10
100
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Receiver Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
Parameter
Min Typ Max Units
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 3)
2.2
5.0
ns
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 3)
2.2
5.0
ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Note 7)(Figure 17) f = 40 MHz
1.0
1.4
2.15
ns
RSPos1 Receiver Input Strobe Position for Bit 1
4.5
5.0
5.8
ns
RSPos2 Receiver Input Strobe Position for Bit 2
8.1
8.5
9.15
ns
RSPos3 Receiver Input Strobe Position for Bit 3
11.6 11.9 12.6
ns
RSPos4 Receiver Input Strobe Position for Bit 4
15.1 15.6 16.3
ns
RSPos5 Receiver Input Strobe Position for Bit 5
18.8 19.2 19.9
ns
RSPos6 Receiver Input Strobe Position for Bit 6
22.5 22.9 23.6
ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Note 6)(Figure 17) f = 66 MHz
0.7
1.1
1.4
ns
RSPos1 Receiver Input Strobe Position for Bit 1
2.9
3.3
3.6
ns
RSPos2 Receiver Input Strobe Position for Bit 2
5.1
5.5
5.8
ns
RSPos3 Receiver Input Strobe Position for Bit 3
7.3
7.7
8.0
ns
RSPos4 Receiver Input Strobe Position for Bit 4
9.5
9.9
10.2
ns
RSPos5 Receiver Input Strobe Position for Bit 5
11.7 12.1 12.4
ns
RSPos6 Receiver Input Strobe Position for Bit 6
13.9 14.3 14.6
ns
RSKM
RxIN Skew Margin (Note 5) (Figure 18)
f = 40 MHz
490
ps
f = 66 MHz
400
ps
RCOP
RxCLK OUT Period (Figure 7)
15
T
50
ns
RCOH
RxCLK OUT High Time (Figure 7)
f = 40 MHz
6.0
10.0
ns
f = 66 MHz
4.0
6.1
ns
RCOL
RxCLK OUT Low Time (Figure 7)
f = 40 MHz
10.0 13.0
ns
f = 66 MHz
6.0
7.8
ns
5
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