DS90CR285 Datasheet, PDF (13/17 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(Note 11) + ISI (Inter-symbol interference)(Note 12)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 11: Cycle-to-cycle jitter is less than 250 ps
Note 12: ISI is dependent on interconnect length; may be zero
01291020
FIGURE 18. Receiver LVDS Input Skew Margin
Pin Descriptions
DS90CR285 MTD56 (TSSOP) Package Pin Description — Channel Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
Description
I
28 TTL level input.
O
4 Positive LVDS differential data output.
O
4 Negative LVDS differential data output.
I
1 TTL IeveI clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
O
1 Positive LVDS differential clock output.
O
1 Negative LVDS differential clock output.
I
1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down.
I
4 Power supply pins for TTL inputs.
I
5 Ground pins for TTL inputs.
I
1 Power supply pin for PLL.
I
2 Ground pins for PLL.
I
1 Power supply pin for LVDS outputs.
I
3 Ground pins for LVDS outputs.
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DWN
V_CC
GND
PLL V_CC
DS90CR286 MTD56 (TSSOP) Package Pin Description — Channel Link Receiver
I/O No.
Description
I
4 Positive LVDS differential data inputs.
I
4 Negative LVDS differential data inputs.
O 28 TTL level data outputs.
I
1 Positive LVDS differential clock input.
I
1 Negative LVDS differential clock input.
O
1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
I
1 TTL level input.When asserted (low input) the receiver outputs are low.
I
4 Power supply pins for TTL outputs.
I
5 Ground pins for TTL outputs.
I
1 Power supply for PLL.
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