DS90C124_08 Datasheet, PDF (5/26 Pages) National Semiconductor (TI) – 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Symbol
t_ROS
t_ROH
t_HZR
t_LZR
t_ZHR
t_ZLR
t_DD
Parameter
ROUT (23:16) Setup Data to
RCLK (Group 3)
ROUT (23:16) Hold Data to
RCLK (Group 3)
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer Delay
Conditions
(Figure 15)
(Figure 13)
(Figure 12)
t_DRDL
Deserializer PLL Lock Time
from Powerdown
RxIN_TOL_L Receiver INput TOLerance
Left,
RxIN_TOL_R Receiver INput TOLerance
Right,
(Figure 14)
(Notes 8, 9)
(Figure 16)
(Notes 7, 9, 11)
(Figure 16)
(Notes 7, 9, 11)
Pin/Freq.
ROUT [23:16]
ROUT [23:0],
RCLK, LOCK
RCLK
5 MHz
35 MHz
5 MHz–35 MHz
5 MHz–35 MHz
Min
Typ
Max Units
(0.40)*
t_RCP
(27/56)*t_RCP
ns
(0.40)*
t_RCP
(29/56)*t_RCP
ns
3
10
ns
3
10
ns
3
10
ns
3
10
ns
[4+(3/56)]T [4+(3/56)]T ns
+5.9
+14
5
50
ms
5
50
ms
0.25
UI
0.25
UI
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Typical values represent most likely parametric norms at V_CC = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 5: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 6: t_DRDL is the time required by the deserializer to obtain lock when exiting powerdown mode. t_DRDL is specified with an external synchronization pattern.
Note 7: RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 8: The Deserializer PLL lock time (t_DRDL) may vary depending on input data patterns and the number of transitions within the pattern.
Note 9: Specification is guaranteed by characterization and is not tested in production.
Note 10: t_JIT (@BER of 10e-9) specifies the allowable jitter on TCLK. t_JIT not included in TxOUT_E_O parameter.
Note 11: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 12: Figures 1, 2, 8, 12, 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 13: Figures 5, 15 show a rising edge data strobe (TCLK IN/RCLK OUT).
Note 14: TxOUT_E_O is affected by pre-emphasis value.
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