DS90C124_08 Datasheet, PDF(17/26 Page) National Semiconductor (TI) – 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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DS90C124_08 Datasheet, PDF (17/26 Pages) National Semiconductor (TI) – 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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used to set each device into power down mode, which re-

duces supply current to the ÂµA range. The Serializer enters

powerdown when the TPWDNB pin is driven low. In power-

down, the PLL stops and the outputs go into TRI-STATE,

disabling load current and reducing supply. To exit Power-

down, TPWDNB must be driven high. When the Serializer

exits Powerdown, its PLL must lock to TCLK before it is ready

for the Initialization state. The system must then allow time for

Initialization before data transfer can begin. The Deserializer

enters powerdown mode when RPWDNB is driven low. In

powerdown mode, the PLL stops and the outputs enter TRI-

STATE. To bring the Deserializer block out of the powerdown

state, the system drives RPWDNB high.

Both the Serializer and Deserializer must reinitialize and re-

lock before data can be transferred. The Deserializer will

initialize and assert LOCK high when it is locked to the input

clock.

TRI-STATE

For the Serializer, TRI-STATE is entered when the DEN or

TPWDNB pin is driven low. This will TRI-STATE both driver

output pins (DOUT+ and DOUTâ). When DEN is driven high,

the serializer will return to the previous state as long as all

other control pins remain static (TPWDNB, TRFB).

When you drive the REN or RPWDNB pin low, the Deserial-

izer enters TRI-STATE. Consequently, the receiver output

pins (ROUT0âROUT23) and RCLK will enter TRI-STATE.

The LOCK output remains active, reflecting the state of the

PLL. The Deserializer input pins are high impedance during

receiver powerdown (RPWDNB low) and power-off (VCC =

0V).

PRE-EMPHASIS

The DS90C241 features a Pre-Emphasis function used to

compensate for long or lossy transmission media. Cable drive

is enhanced with a user selectable Pre-Emphasis feature that

provides additional output current during transitions to coun-

teract cable loading effects. The transmission distance will be

limited by the loss characteristics and quality of the media.

Pre-Emphasis adds extra current during LVDS logic transition

to reduce the cable loading effects and increase driving dis-

tance. In addition, Pre-Emphasis helps provide faster transi-

tions, increased eye openings, and improved signal integrity.

To enable the Pre-Emphasis function, the âPREâ pin requires

one external resistor (Rpre) to Vss in order to set the addi-

tional current level. Pre-Emphasis strength is set via an ex-

ternal resistor (Rpre) applied from min to max (floating to

3kâ¦) at the âPREâ pin. A lower input resistor value on the

âPREâ pin increases the magnitude of dynamic current during

data transition. There is an internal current source based on

the following formula: PRE = (Rpre â¥ 3kâ¦); IMAX = [(1.2/Rpre)

X 20]. The ability of the DS90C241 to use the Pre-Emphasis

feature will extend the transmission distance up to 10 meters

in most cases.

The amount of Pre-Emphasis for a given media will depend

on the transmission distance of the application. In general, too

much Pre-Emphasis can cause over or undershoot at the re-

ceiver input pins. This can result in excessive noise, crosstalk

and increased power dissipation. For short cables or dis-

tances, Pre-Emphasis may not be required. Signal quality

measurements are recommended to determine the proper

amount of Pre-Emphasis for each application.

AC-COUPLING AND TERMINATION

The DS90C241 and DS90C124 supports AC-coupled inter-

connects through integrated DC balanced encoding/decoding

scheme. To use AC coupled connection between the Serial-

izer and Deserializer, insert external AC coupling capacitors

in series in the LVDS signal path as illustrated in Figure 17.

The Deserializer input stage is designed for AC-coupling by

providing a built-in AC bias network which sets the internal

VCM to +1.2V. With AC signal coupling, capacitors provide the

ac-coupling path to the signal input.

For the high-speed LVDS transmissions, the smallest avail-

able package should be used for the AC coupling capacitor.

This will help minimize degradation of signal quality due to

package parasitics. The most common used capacitor value

for the interface is 100 nF (0.1 uF) capacitor. NPO class 1 or

X7R class 2 type capacitors are recommended. 50 WVDC

should be the minimum used for the best system-level ESD

performance.

The DS90C124 input stage is designed for AC-coupling by

providing a built-in AC bias network which sets the internal

VCM to +1.2V. Therefore multiple termination options are

possible.

Receiver Termination Option 1

A single 100 Ohm termination resistor is placed across the

RINÂ± pins (see Figure 17). This provides the signal termina-

tion at the Receiver inputs. Other options may be used to

increase noise tolerance.

Receiver Termination Option 2

For additional EMI tolerance, two 50 Ohm resistors may be

used in place of the single 100 Ohm resistor. A small capacitor

is tied from the center point of the 50 Ohm resistors to ground

(see Figure 20). This provides a high-frequency low

impedance path for noise suppression. Value is not critical,

4.7nF maybe used with general applications.

Receiver Termination Option 3

For high noise environments an additional voltage divider

network may be connected to the center point. This has the

advantage of a providing a DC low-impedance path for noise

the pullup and pulldown. Ratio the resistor values to bias the

center point at 1.2V. For example (see Figure 21): VDD=3.3V,

more bias current, but will provide enhanced noise suppres-

sion.

PROGRESSIVE TURNâON (PTO)

Deserializer ROUT[23:0] outputs are grouped into three

groups of eight, with each group switching about 0.5UI apart

in phase to reduce EMI, simultaneous switching noise, and

system ground bounce.

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