DS90C124_08 Datasheet, PDF (4/26 Pages) National Semiconductor (TI) – 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
t_TCP
t_TCIH
t_TCIL
t_CLKT
t_JIT
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
(Figure 5)
(Figure 4)
(Note 10)
Min Typ Max Units
28.6 T 200 ns
0.4T 0.5T 0.6T ns
0.4T 0.5T 0.6T ns
3 6 ns
33
ps
(RMS)
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
t_LLHT
t_LHLT
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
R_L = 100Ω, (Figure 3)
C_L = 10 pF to GND
VODSEL = L
t_DIS
DIN (23:0) Setup to TCLK
R_L = 100Ω,
5
t_DIH
DIN (23:0) Hold from TCLK
C_L = 10 pF to GND
(Note 9)
5
t_HZD
DOUT ± HIGH to TRI-STATE Delay
R_L = 100Ω,
t_LZD
DOUT ± LOW to TRI-STATE Delay
C_L = 10 pF to GND
t_ZHD
DOUT ± TRI-STATE to HIGH Delay
(Figure 6) (Note 5)
t_ZLD
DOUT ± TRI-STATE to LOW Delay
t_PLD
Serializer PLL Lock Time
R_L = 100Ω, (Figure 7)
t_SD
Serializer Delay
R_L = 100Ω, (Figure 8)
VODSEL = L, TRFB = H
R_L = 100Ω, (Figure 8)
VODSEL = L, TRFB = L
TxOUT_E_O
TxOUT_Eye_Opening
(respect to ideal)
5–35 MHz
(Figure 9)
0.75
(Notes 9, 10, 14)
Typ
3.5T + 2.85
3.5T + 2.85
Max Units
0.6
ns
0.6
ns
ns
ns
15
ns
15
ns
200
ns
200
ns
10
ms
3.5T
+ 10
ns
3.5T
+ 10
ns
UI
(Note 11)
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max Units
t_RCP
Receiver out Clock Period
t_RCP = t_TCP
RCLK
(Note 9)
28.6
200
ns
t_RDC
RCLK Duty Cycle
RCLK
45
50
55
%
t_CLH
LVCMOS Low-to-High
C_L = 8 pF
ROUT [23:0],
Transition Time
(lumped load)
LOCK, RCLK
2.5
3.5
ns
t_CHL
LVCMOS High-to-Low
(Figure 11)
Transition Time
(Note 9)
2.5
3.5
ns
t_ROS
ROUT (7:0) Setup Data to
RCLK (Group 1)
(Figure 15)
ROUT [7:0]
(0.40)*
t_RCP
(29/56)*t_RCP
ns
t_ROH
ROUT (7:0) Hold Data to RCLK
(Group 1)
(0.40)*
t_RCP
(27/56)*t_RCP
ns
t_ROS
ROUT (15:8) Setup Data to
RCLK (Group 2)
(Figure 15)
ROUT [15:8],
LOCK
(0.40)*
t_RCP
0.5*t_RCP
ns
t_ROH
ROUT (15:8) Hold Data to
RCLK (Group 2)
(0.40)*
t_RCP
0.5*t_RCP
ns
www.national.com
4