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DS90C124_08 Datasheet, PDF (3/26 Pages) National Semiconductor (TI) – 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
Symbol
Parameter
Conditions
Pin/Freq.
VOD
Output Differential Voltage
RL = 100Ω, w/o Pre-emphasis
Tx: DOUT+, DOUT−
(DOUT+)–(DOUT−)
VODSEL = L (Figure 10)
RL = 100Ω, w/o Pre-emphasis
VODSEL = H (Figure 10)
ΔVOD
Output Differential Voltage
Unbalance
RL = 100Ω, w/o Pre-emphasis
VOS
ΔVOS
IOS
Offset Voltage
Offset Voltage Unbalance
Output Short Circuit Current
RL = 100Ω, w/o Pre-emphasis
RL = 100Ω, w/o Pre-emphasis
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = L
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = H
IOZ
TRI-STATE Output Current TPWDNB, DEN = 0V,
DOUT = 0V or 2.4V
SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins) *Digital, PLL, and Analog VDDs
ICCT
Serializer (Tx)
Total Supply Current
(includes load current)
RL = 100Ω
RPRE = OFF
VODSEL = H/L
Checker-board pattern (Figure 1)
f = 35 MHz
RL = 100Ω
RPRE = 6 kΩ
VODSEL = H/L
Checker-board pattern (Figure 1)
f = 35 MHz
Serializer (Tx)
Total Supply Current
(includes load current)
RL = 100Ω
RPRE = OFF
VODSEL = H/L
f = 35 MHz
RL = 100Ω
RPRE = 6 kΩ
VODSEL = H/L
Random pattern
f = 35 MHz
ICCTZ
Serializer (Tx)
TPWDNB = 0V
Supply Current Power-down (All other LVCMOS Inputs = 0V)
ICCR
Deserializer (Rx)
Total Supply Current
(includes load current)
CL = 8 pF LVCMOS Output
Checker-board pattern
(Figure 2)
f = 35 MHz
Deserializer (Rx)
Total Supply Current
(includes load current)
CL = 8 pF LVCMOS Output
Random pattern
f = 35 MHz
ICCRZ
Deserializer (Rx)
Supply Current Power-down
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
RIN+/ RIN- = 0V)
Min Typ Max Units
250 400 600 mV
450 750 1200 mV
10 50 mV
1.00 1.25 1.50 V
1 50 mV
−2
−8 mA
−7
−13 mA
−15 ±1 +15 µA
40 65 mA
45 70 mA
40 65 mA
45 70 mA
800 µA
85 mA
80 mA
50 µA
3
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