DS90C124_08 Datasheet, PDF (19/26 Pages) National Semiconductor (TI) – 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

lines help to ensure that coupled noise will appear as com-
mon-mode and thus is rejected by the receivers. The tightly
coupled lines will also radiate less.
Termination of the LVDS interconnect is required. For point-
to-point applications, termination should be located at both
ends of the devices. Nominal value is 100 Ohms to match the
line’s differential impedance. Place the resistor as close to the
transmitter DOUT± outputs and receiver RIN± inputs as pos-
sible to minimize the resulting stub between the termination
resistor and device.
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
—S = space between the pair
—2S = space between pairs
—3S = space to LVCMOS/LVTTL signal
• Minimize the number of VIA
• Use differential connectors when operating above
500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as
possible
Additional general guidance can be found in the LVDS
Owner’s Manual - available in PDF format from the National
web site at: www.national.com/lvds
FIGURE 17. AC Coupled Application
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