COP87L88CL Datasheet, PDF (4/34 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable OTP Microcontroller

Absolute Maximum Ratings (Note)
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Supply Voltage (V_CC)
Voltage at Any Pin
Total Current into V_CC Pin (Source)
7V
b0 3V to V_CC a 0 3V
100 mA
Total Current out of GND Pin (Sink)
110 mA
Storage Temperature Range
b65 C to a140 C
Note Absolute maximum ratings indicate limits beyond which damage to the
device may occur DC and AC electrical specifications are not ensured when
operating the device at absolute maximum ratings
DC Electrical Characteristics b40 C ^s T_A ^s a85 C unless otherwise specified
Parameter
Conditions
Min
Typ
Operating Voltage
27
Power Supply Ripple (Note 1)
Peak-to-Peak
Supply Current (Note 2)
CKI e 10 MHz
CKI e 4 MHz
HALT Current (Note 3)
IDLE Current CKI e 10 MHz
CKI e 1 MHz
Input Levels
RESET
Logic High
Logic Low
CKI (External and Crystal Osc Modes)
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
V_CC e 5 5V t_c e 1 ms
V_CC e 4 0V t_c e 2 5 ms
V_CC e 5 5V CKI e 0 MHz
V_CC e 5 5V t_c e 1 ms
V_CC e 4 0V t_c e 10 ms
0 8 V_CC
0 7 V_CC
0 7 V_CC
Hi-Z Input Leakage
Input Pullup Current
G and L Port Input Hysteresis
Output Current Levels
D Outputs
Source
Sink (Note 4)
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
Allowable Sink Source
Current per Pin
D Outputs (Sink)
All others
V_CC e 5 5V
V_CC e 5 5V
V_CC e 4 5V V_OH e 3 3V
V_CC e 4 5V V_OL e 1V
V_CC e 4 5V V_OH e 2 7V
V_CC e 4 5V V_OH e 3 3V
V_CC e 4 5V V_OL e 0 4V
V_CC e 5 5V
b2
40
0 05 V_CC
04
10
10
04
16
b2
Maximum Input Current
without Latchup (Note 5)
T_A e 25 C
RAM Retention Voltage V_r
500 ns Rise
and Fall Time (Min)
2
Input Capacitance
Load Capacitance on D2
Max
55
0 1 V_CC
16 5
65
12
35
07
0 2 V_CC
0 2 V_CC
0 2 V_CC
a2
250
0 35 V_CC
100
a2
15
3
g100
7
1000
Units
V
V
mA
mA
mA
mA
mA
V
mA
mA
V
mA
mA
mA
mA
mA
mA
mA
mA
V
pF
pF
Note 1 Rate of voltage change must be less then 0 5V ms
Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open
Note 3 The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high Test conditions All inputs tied to V_CC L and G
ports in the TRI-STATE mode and tied to ground all outputs low and tied to ground The clock monitor is disabled
Note 4 The user must guarantee that D2 pin does not source more than 10 mA during RESET If D2 sources more than 10 mA during RESET the device will go
into programming mode
Note 5 Pins G5 and RESET are designed with a high voltage input network for factory testing These pins allow input voltages greater than V_CC and the pins will
have sink current to V_CC when biased at voltages greater than V_CC (the pins do not have source current when biased at a voltage below V_CC) The effective
resistance to V_CC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V
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