COP87L88CL Datasheet, PDF (15/34 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable OTP Microcontroller

Interrupts (Continued)
Arbitration
Ranking
(1) Highest
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16) Lowest
Source
Software
Reserved
External
Timer T0
Timer T1
Timer T1
MICROWIRE PLUS
Reserved
Reserved
Reserved
Timer T2
Timer T2
Reserved
Reserved
Port L Wakeup
Default
y is VIS page y i 0
Two bytes of program memory space are reserved for each
interrupt source All interrupt sources except the software
interrupt are maskable Each of the maskable interrupts
have an Enable bit and a Pending bit A maskable interrupt
is active if its associated enable and pending bits are set If
GIE e 1 and an interrupt is active then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine This exception is described
in the Software Trap sub-section
The interruption process is accomplished with the INTR in-
struction (opcode 00) which is jammed inside the Instruc-
tion Register and replaces the opcode about to be execut-
ed The following steps are performed for every interrupt
1 The GIE (Global Interrupt Enable) bit is reset
2 The address of the instruction about to be executed is
pushed into the stack
3 The PC (Program Counter) branches to address 00FF
This procedure takes 7 t_c cycles to execute
Description
INTR Instruction
for Future Use
Pin G0 Edge
Underflow
T1A Underflow
T1B
BUSY Goes Low
for Future Use
for UART
for UART
T2A Underflow
T2B
for Future Use
for Future Use
Port L Edge
VIS Instr Execution
without Any Interrupts
Vector
Address
Hi-Low Byte
0yFE – 0yFF
0yFC – 0yFD
0yFA – 0yFB
0yF8 – 0yF9
0yF6 – 0yF7
0yF4 – 0yF5
0yF2 – 0yF3
0yF0 – 0yF1
0yEE – 0yEF
0yEC – 0yED
0yEA – 0yEB
0yE8 – 0yE9
0yE6 – 0yE7
0yE4 – 0yE5
0yE2 – 0yE3
0yE0 – 0yE1
At this time since GIE e 0 other maskable interrupts are
disabled The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions The user would then pro-
gram a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS Note
that this is not necessarily the interrupt that caused the
branch to address location 00FF Hex prior to the context
switching
Thus if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS then the
interrupt with the higher rank will override any lower ones
and will be acknowledged The lower priority interrupt(s) are
still pending however and will cause another interrupt im-
mediately following the completion of the interrupt service
routine associated with the higher priority interrupt just serv-
iced This lower priority interrupt will occur immediately fol-
lowing the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed
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