COP87L88CL Datasheet, PDF (19/34 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable OTP Microcontroller

Detection of Illegal
Conditions (Continued)
The subroutine stack grows down for each call (jump to
subroutine) interrupt or PUSH and grows up for each re-
turn or POP The stack pointer is initialized to RAM location
06F Hex during reset Consequently if there are more re-
turns than calls the stack pointer will point to addresses
070 and 071 Hex (which are undefined RAM) Undefined
RAM from addresses 070 to 07F Hex is read as all 1’s
which in turn will cause the program to return to address
7FFF Hex This is an undefined ROM location and the in-
struction fetched (all 0’s) from this location will generate a
software interrupt signaling an illegal condition
Thus the chip can detect the following illegal conditions
1 Executing from undefined ROM
2 Over ‘‘POP’’ing the stack by having more returns than
calls
When the software interrupt occurs the user can re-initialize
the stack pointer and do a recovery procedure before re-
starting (this recovery program is probably similar to that
following reset but might not contain the same program
initialization procedures)
MICROWIRE PLUS
MICROWIRE PLUS is a serial synchronous communica-
tions interface The MICROWIRE PLUS capability enables
the device to interface with any of National Semiconductor’s
MICROWIRE peripherals (i e A D converters display driv-
ers E²PROMs etc ) and with other microcontrollers which
support the MICROWIRE interface It consists of an 8-bit
serial shift register (SIO) with serial data input (SI) serial
data output (SO) and serial shift clock (SK) Figure 11
shows a block diagram of the MICROWIRE logic
The shift clock can be selected from either an internal
source or an external source Operating the MICROWIRE
PLUS arrangement with the internal clock source is called
the Master mode of operation Similarly operating the
MICROWIRE PLUS arrangement with an external shift
clock is called the Slave mode of operation
TL DD 12524 – 14
FIGURE 11 MICROWIRE PLUS Block Diagram
The CNTRL register is used to configure and control the
MICROWIRE PLUS mode To use the MICROWIRE PLUS
the MSEL bit in the CNTRL register is set to one In the
master mode the SK clock rate is selected by the two bits
SL0 and SL1 in the CNTRL register Table VI details the
different clock rates that may be selected
MICROWIRE PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE PLUS to start shifting the data It gets reset
when eight data bits have been shifted The user may reset
the BUSY bit by software to allow less than 8 bits to shift If
enabled an interrupt is generated when eight data bits have
been shifted The device may enter the MICROWIRE PLUS
mode either as a Master or as a Slave Figure 12 shows
how two COP888 microcontrollers and several peripherals
may be interconnected using the MICROWIRE PLUS ar-
rangements
Warning
The SIO register should only be loaded when the SK clock
is low Loading the SIO register while the SK clock is high
will result in undefined data in the SIO register SK clock is
normally low when not shifting
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow For safety the
BUSY flag should only be set when the input SK clock is
low
MICROWIRE PLUS Master Mode Operation
In the MICROWIRE PLUS Master mode of operation the
shift clock (SK) is generated internally The MICROWIRE
Master always initiates all data exchanges The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register Table VII summarizes the bit settings
required for Master mode of operation
MICROWIRE PLUS Slave Mode Operation
In the MICROWIRE PLUS Slave mode of operation the SK
clock is generated by an external source Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bit in the Port G configuration reg-
ister Table VII summarizes the settings required to enter
the Slave mode of operation
The user must set the BUSY flag immediately upon entering
the Slave mode This will ensure that all data bits sent by
the Master will be shifted properly After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated
Alternate SK Phase Operation
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register
In both the modes the SK is normally low In the normal
mode data is shifted in on the rising edge of the SK clock
and the data is shifted out on the falling edge of the SK
clock The SIO register is shifted on each falling edge of the
SK clock in the normal mode In the alternate SK phase
mode the SIO register is shifted on the rising edge of the SK
clock
A control flag SKSEL allows either the normal SK clock or
the alternate SK clock to be selected Resetting SKSEL
causes the MICROWIRE PLUS logic to be clocked from the
normal SK signal Setting the SKSEL flag selects the alter-
nate SK clock The SKSEL is mapped into the G6 configura-
tion bit The SKSEL flag will power up in the reset condition
selecting the normal SK signal
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