NSBMC290-16 Datasheet, PDF (3/20 Pages) National Semiconductor (TI) – Burst Mode Memory Controller

Pin Descriptions
PGA Pin
J2
J1
L2
M3
N1
K1
L3
M1
K2
L1
H2
H1
G2
G1
F1
F3
F2
E1
E2
D1
D2
C1
E3
B1
C2
D3
A1
B2
A2
B3
C4
C3
K11
N13
L12
M13
K13
J12
J13
J11
H11
QFP Pin
6
5
11
21
12
7
20
10
8
9
3
2
132
131
129
130
128
126
125
124
123
122
127
121
120
118
119
112
110
111
113
115
53
54
55
56
59
60
61
62
65
Signal
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
PGA Pin
G13
G12
C11
B11
A12
A11
B9
A9
C9
B8
A7
B7
C7
N6
F11
E13
E12
D13
A5
B5
A4
B4
L8
M10
N12
L6
N10
N11
M9
M5
L4
M4
N8
N7
M11
M12
M8
M6
N2
B13
B12
QFP Pin
66
67
87
88
89
90
93
94
95
96
99
100
101
30
71
72
73
74
105
106
107
108
37
41
43
31
40
42
39
26
19
24
35
32
44
45
36
29
22
77
80
Signal
AA9
AA10
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
BINV
CASA0
CASA1
CASA2
CASA3
CASB0
CASB1
CASB2
CASB3
DBACK
DBLEA
DBLEB
DBREQ
DBTXA
DBTXB
DRDY
DREQ
DREQT0
DREQT1
IBACK
IBREQ
IBTXA
IBTXB
IRDY
IREQ
IREQT
MWEA
MWEB
PGA Pin
K3
M2
N3
L5
N9
N5
N4
G11
A6
A13
C12
D11
L7
G3
L10
J3
A3
A8
B6
B10
D12
E11
F13
H3
H12
L9
L13
A10
C5
C6
C8
C10
C13
F12
H13
K12
L11
M7
QFP Pin
15
13
23
28
38
27
25
68
102
78
79
82
34
1
46
14
4
47
57
63
69
75
81
91
97
103
109
33
48
58
64
70
76
86
92
98
104
114
Signal
OPT0
OPT1
OPT2
PDA
PEN
PIA
RW
RASA
RASB
Reserved
Reserved
Reserved
Reserved
RESET
RSTOUT
SYSCLK
V_CC
V_CC
V_CC
V_CC
V_CC
V_CC
V_CC
V_CC
V_CC
V_CC
V_CC
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
Note In order for the switching characteristics of this device to be guaranteed it is necessary to connect all of the power pins (V_CC V_SS) to the appropriate power
levels The use of low impedance wiring to the power pins is required In systems using the Am29000 with its attendant high switching rates multi-layer printed
circuit boards with buried power and ground planes are required
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