NSBMC290-16 Datasheet, PDF (15/20 Pages) National Semiconductor (TI) – Burst Mode Memory Controller

AC Timing Parameters (Unless otherwise stated V_CC e 5 0V g5% 0 C ^k T_A ^k 70 C )
Symbol
Description
16 MHz
20 MHz
25 MHz
33 MHz _Units
Min Max Min Max Min Max Min Max
1 t_BSU
2 t_BH
3 t_RQSU
4 t_RQH
5 t_SU
5A t_SU
6 t_H
6A t_BRH
7 t_ARA
8 t_RAH
8A t_DRAH
9 t_CAV
BlNV Setup
BINV Hold
Request Sync Setup Time
Request Sync Hold Time
Synchronous Input Setup
Synchronous Input Setup I DBREQ only
Synchronous Input Hold
SYSCLK to Burst Request Input Hold
Address Input to Row Address output delay
(Note 1)
SYSCLK to row address hold
DRAM Row Address Hold (Note 2)
SYSCLK to Column Address Valid Delay
(Note 1)
8
7
6
5
ns
4
3
3
2
ns
17
13
12
10
ns
4
3
3
2
ns
17
13
12
10
ns
9
8
6
45
ns
4
3
3
2
ns
4
3
3
2
ns
29
24
22
18 ns
9
8
7
6
ns
t_CLK-4
t_CLK-4
t_CLK-3
t_CLK-2
ns
38
32
29
24 ns
10 t_CAH
11 t_RSHL
12 t_RSLH
13 t_CHL
14 t_CLH
15 t_PZH
SYSCLK to Column Address Hold
SYSCLK to RAS Asserted Delay (Note 1)
SYSCLK to RAS De-asserted Delay (Note 1)
SYSCLK to CAS Asserted Delay (Note 1)
SYSCLK to CAS De-asserted (Note 1)
PEN 3-state to Valid Delay Relative to
SYSCLK
6
6
5
5
ns
26
22
20
17 ns
23
19
17
14 ns
32
27
24
20 ns
40
33
30
25 ns
30
25
23
19 ns
16 t_PHL
17 t_PLH
18 t_PHZ
19 t_RZH
20 t_RHL
21 t_RLH
PEN Synchronous Assertion Delay
PEN Synchronous Deassertion Delay
PEN Valid to 3-state Delay Relative to
SYSCLK
RDY 3-state to Valid Delay Relative to
SYSCLK
RDY Synchronous Assertion Delay
RDY Synchronous De-assertion Delay
26
22
20
17 ns
25
21
19
16 ns
29
24
22
18 ns
30
25
23
19 ns
26
22
20
17 ns
25
21
19
16 ns
22 t_RHZ
RDY Valid to 3-state Delay Relative to
SYSCLK
29
24
22
18 ns
23 t_LEHL Synchronous Latch Enable Assertion delay
32
27
24
20 ns
24 t_LELH Synchronous Latch Enable De-assertion Delay
42
35
32
26 ns
25 t_BHL Synchronous Buffer Enable Assertion Delay
49
41
37
31 ns
26 t_BLH Synchronous Buffer Enable De-assertion Delay
38
32
29
24 ns
27 t_RWSU Synchronous R W Input Setup Time
8
7
6
5
ns
28 t_RWH
29 t_WEV
30 t_BKZH
31 t_BKHL
32 t_BKLH
33 t_BKHZ
34 t_ABKLH
Synchronous R W Input Hold Time
Synchronous Write Enable Valid Delay
Relative to SYSCLK
Synchronous I DBACK Valid Delay
Synchronous I DBACK Assertion Delay
Synchronous I DBACK Deassertion Delay
Synchronous I DBACK Valid to 3-state Delay
Asynchronous I DBACK Deassertion delay
relative to I DREQ
4
3
3
2
ns
59
49
44
37 ns
25
21
19
16 ns
29
24
22
18 ns
24
20
18
15 ns
24
20
18
15 ns
22
18
14
12 ns
Signal output delays are measured relative to SYSCLK (except as indicated) using a 50 pF load
Note 1 Derate the given delays by 0 06 ns per pF of load in excess of 50 pF
Note 2 Where t_CLK e 1 (2 Clock Frequency)
15