NSBMC290-16 Datasheet, PDF (11/20 Pages) National Semiconductor (TI) – Burst Mode Memory Controller

CPU INTERFACE
The NSBMC290 interface to the Am29000 has been de-
signed for direct interconnect Normally it is not necessary
to place other logic devices between the processor
NSBMC290 and memory with the exception of Instruction
Data bus buffers The introduction of intermediate buffers
can result in skews or delays that will require that the sys-
tem clock frequency be derated for operation under worst
case conditions
SIMPLE ACCESS SEQUENCE
The NSBMC290 can return data to the processor in only 4
clocks or 5 clocks for a simple access depending on the
mode chosen (Configuration Bit 17) If multiple access
cycles are requested back to back then the BMC will pause
for a minimum of 2 clocks between RAS cycles to insure
that the RAS precharge time is met resulting in 5 clocks or 6
clocks between successive simple cycles (depending on
Configuration bit 17)
All access modes begin their cycle in the same fashion as a
simple access A simple access can become either a pipe-
lined or burst access if the appropriate inputs are driven
Figure 3 shows the timing relationship between the system
clock processor control signals and NSBMC290 outputs
All NSBMC290 outputs are derived synchronously with the
exception of t_ARA7 (processor address to memory address
delay) The shaded section in Figure 3 represents the extra
cycle inserted when the configuration register is initialized
with bit 17 cleared
DBTX DBTXa DBTXb DBCE DBCEa DBCEb IBTX IBTXa IBTXb
FIGURE 3 Simple Access Sequence
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