NSBMC290-16 Datasheet, PDF (1/20 Pages) National Semiconductor (TI) – Burst Mode Memory Controller

July 1993
NSBMC290^TM-16 -20 -25 -33
Burst Mode Memory Controller
General Description
The NSBMC290 is functionally equivalent to the
V29BMC^TM The NSBMC290 Burst Mode Memory Control-
ler is a single chip device designed to simplify the imple-
mentation of burst mode access in high performance sys-
tems using the Am29000^TM Streamlined Instruction Proces-
sor
The extremely high instruction rate achieved by this proces-
sor places extraordinary demands on memory system de-
signs if maximum throughput is to be sustained and costs
minimized
The most obvious solution to the problem of access speed
is to implement system memory using high-speed static
memories However the high cost and low density of these
devices make them an expensive and space consumptive
solution
A more cost effective method of solving this problem is via
the use of dynamic RAMs Their high density and low cost
make their use extremely attractive The impediment to their
use is their relatively slow access times
However when operated in page mode dynamic RAMs be-
have more like static memories Properly managed they
can yield access times approaching those of fully static
RAMs
Block Diagram
Typical System Configuration
The function of NSBMC290 is to interface the page mode
access protocol of dynamic RAMs with the more general
burst mode access protocol supported by the Am29000 lo-
cal channel The device manages a double banked arrang-
ment of dynamic RAMs such that when burst accesses are
permitted data can be read or written at the rate of one
word per system clock cycle
Packaged as a 124 pin PGA or 132 pin PQFP the
NSBMC290 drives memory arrays directly thus minimizing
design complexity and package count
Features
Y _{Interfaces directly to Am29000 Local Channel}
Y _{Manages Page Mode Dynamic Memory devices}
Y _{Supports DRAMs from 64 KB to 16 MB}
Y _{Manages Instruction and or Data Memory}
Y _{Very Low Power Consumption}
Y _{On-Chip Memory Address Multiplexer Drivers}
Y _{Flexible Instruction Data Bus Buffer Management}
Y _{Software-Configured operational parameters}
Y _{Auto-Configured Bank Size and Location}
Y _{High-Speed CMOS Technology}
Logic Symbol
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This document contains information concerning a product that has been developed by National Semiconductor Corporation V3 Corporation This information
is intended to help in evaluating this product National Semiconductor Corporation V3 Corporation reserves the right to change and improve the specifications
of this product without notice
TRI-STATE is a registered trademark National Semiconductor Corporation
NSBMC290TM is a trademark of National Semiconductor Corporation
V29BMCTM is a trademark of V3 Corporation
Am29000TM is a trademark of Advanced Micro Devices Sunnyvale California USA
C1995 National Semiconductor Corporation TL V 11803
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