NSBMC290-16 Datasheet, PDF (17/20 Pages) National Semiconductor (TI) – Burst Mode Memory Controller

Release Notes for NSBMC290
Revision ‘‘A’’
A NOTE ON THE OPERATION OF THE Am29000
It is a characteristic of the Am29000 (Rev D) that it can de-
assert the IBREQ signal independently of the current state
of IRDY and IBACK The V29BMC (Rev A) accommo-
dates this behavior in all cases with one exception
ERRATUM 1
If IBREQ is de-asserted 1 or two clock cycles before
IRDY is returned and the instruction access cycle is fol-
lowed in the next clock cycle by a data write the write en-
able signals from the V29BMC to memory are asserted
clock cycle before RAS CAS are de-asserted The mem-
ory location following the last completed instruction access
may be corrupted
RECOMMENDED FIX
The ‘‘write enables’’ to memory must be delay by a clock
cycle This may be achieved in the following ways
1 The RAS signals may be used to latch the write enable
from the V29BMC as shown in Figure 7
2 The write enable into the V29BMC may be delayed See
Figure 8
FIGURE 7
TL V 11803 – 11
The logic shown in Figure 7 can be implemented in a PAL
using the following positive true logic equation
WEa e RASa MWE
RASa WEA
MWE is MWEa or MWEb since they are identical
The primary difference between the two recommended so-
lutions is that the one given in Figure 8 makes use of the
high current drivers on the V29BMC for driving the write
enable signal to the memory array For systems using bit
organized memories this type of drive capability is desired
The ‘‘or’’ function implemented by the ’F32 may be moved
inside the PAL by appropriately modifying the equations For
maximum performance it should be a discrete gate as
shown
This modification is only required for a V29BMC controlling
memories from which instructions are being run This modifi-
cation however implemented will affect the timing of Pipe-
line Cycles Do not connect PEN to a V29BMC whose write
timing is modified and connect PIA PDA only to a pull-up
resistor For a V29BMC controlling data only memory no
changes to the write enable timing are required and pipeline
access may be used Using data pipelining performance
improvements of the order of 2% have been observed
ERRATUM 2
If buffer mode 3 (or 1) is selected then it is possible for
DBCE(a b) to be asserted during a refresh cycle This will
happen if a data write cycle not accessing the BMC is fol-
lowed in the next cycle by a read cycle also not accessing
the BMC such that refresh on the BMC starts with the read
The result is that the data bus can be driven by the buffers
controlled by the V29BMC when other devices are using it
RECOMMENDED FIX
There are a number of possible fixes of which 2 are outlined
below The first solution is to use the mode 2 (or 0) buffer
control signals and generate a DBCE(a b) signal from
WE(a b) and DBTX(a b) Make sure that mode 2(or 0) op-
eration is selected in the V29BMC configuration word
TL V 11803 – 13
FIGURE 9 Generation of DBCE
from WE and DBTX Signals
The second solution is to use the DBCE(a b) signal and
qualify it using the DBLE signals as shown below
FIGURE 8
TL V 11803 – 12
The PAL shown in Figure 8 can be programmed with one of
the two following equations depending on which of the two
dotted paths is connected
RD ONLY d e RASa RASb BMC R W
or
RD ONLY d e RASa RASb IREQ
17
TL V 11803 – 14
FIGURE 10 Modification of DBCE Signal
Using the V29BMC Latch Enable Signals