NSBMC290-16 Datasheet, PDF (16/20 Pages) National Semiconductor (TI) – Burst Mode Memory Controller

AC Timing Parameters (Continued)
TL V 11803 – 7
TXa e IBTXa DBTXa CEa e IBCEa DBCE TXb e IBTXb DBTXb CEb e IBCEb DBCEb and BANKb a
Note Buffer control signal timing is illustrated using the mode dependent signal naming convention (See page 7 ) As shown the switching behavior is typical of
modes 0 and 1 In modes 2 and 3 the timing of signals DBTX DBCE and IBTX remain unchanged
FIGURE 6 Burst Access Timing
TABLE VIII Burst Access Timing Parameters
Symbol
Description
16 MHz
20 MHz
25 MHz
33 MHz
Units
Min Max Min Max Min Max Min Max
1 t_CHL
2 t_CLH
3 t_CAV
4 t_CAH
5 t_BHL
6 t_BLH
7 t_LEHL
8 t_LELH
SYSCLK to CAS Assertion (Note 1)
25
21
19
15 5 ns
SYSCLK to CAS De-Assertion (Note 1)
24
20
18
15 ns
SYSCLK to Column Address Valid Delay (Note 1)
38
32
29
24 ns
SYSCLK to Column Address Hold Time (Note 1) 6 34 5 28 5 25 3 21 ns
SYSCLK to Buffer Control Assertion Delay
25
21
19
15 5 ns
SYSCLK to Buffer Control De-Assertion Delay
24
20
18
15 ns
SYSCLK to Latch Enable Assertion
26
22
20
16 5 ns
SYSCLK to Latch Enable De-Assertion
26
22
20
16 5 ns
Signal output delays are measured relative to SYSCLK (except as indicated) using a 50 pF load
Note 1 Derate given the delays by 0 06 ns per pF or load in excess of 50 pF
16