DS92LV2421 Datasheet, PDF (28/40 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

OSC_SEL2
L
L
L
L
H
H
H
H
TABLE 9. OSC_SEL (Oscillator) Configuration
OSC_SEL[2:0] INPUTS
OSC_SEL1
L
L
H
H
L
L
H
H
OSC_SEL0
L
H
L
H
L
H
L
H
CLKOUT Oscillator Frequency
Off – Feature Disabled – Default
50 MHz ±40%
25 MHz ±40%
16.7 MHz ±40%
12.5 MHz ±40%
10 MHz ±40%
8.3 MHz ±40%
6.3 MHz ±40%
FIGURE 23. Des Outputs with Output State High and CLK Output Oscillator Option Enabled
30110154
Des — OP_LOW — Optional
The OP_LOW feature is used to hold the LVCMOS outputs,
except for the LOCK output, at a LOW state. When the
OP_LOW feature is enabled, the LVCMOS outputs will be
held at logic LOW while LOCK = LOW. The user must toggle
the OP_LOW Set/Reset register bit to release the outputs to
the normal toggling state. Note that the release of the outputs
can only occur when LOCK is HIGH. The OP_LOW strap op-
tion is assigned to the PASS pin, at pin location 42.
Restrictions on other straps:
1. Other strap options should not be used in order to keep
the data and clock outputs at a true logic LOW state.
Other features should be selected through the I2C
register interface.
2. The OSS_SEL feature is not available when OP_LOW is
enabled.
Outputs DO[23:0], CO[3:1] and CLKOUT are in TRI-STATE™
before PDB toggles HIGH because the OP-LOW strap value
has not been recognized until the DS92LV2422 powers up.
Figure 24 shows the user controlled release of the OP_LOW
and automatic reset of OP_LOW set on the falling edge of
LOCK. Figure 25 shows the user controlled release of
OP_LOW and manual reset of OP_LOW set. Note manual
reset of OP_LOW can only occur when LOCK is HIGH.
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