DS92LV2421 Datasheet, PDF (24/40 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

quality on the link with an integrated equalizer on the serial
input and Channel Link II data encoding which provides ran-
domization, scrambling, and DC balanacing of the data. The
Des includes multiple features to reduce EMI associated with
data transmission. This includes the randomization and
scrambling of the data, the output spread spectrum clock
generation (SSCG) support and output clock and data slew
rate select. The Des features power saving features with a
power down mode, and optional LVCMOS (1.8 V) interface
compatibility.
Integrated Signal Conditioning Features — Des
Des — Input Equalizer Gain (EQ)
The Des can enable receiver input equalization of the serial
stream to increase the eye opening to the Des input. Note this
function cannot be seen at the RxIN+/- input but can be ob-
served at the serial test port (ROUT+/-) enabled via the Serial
Bus control registers. The equalization feature may be con-
trolled by the external pin or by register.
TABLE 4. Receiver Equalization Configuration Table
EQ3
INPUTS
EQ2
EQ1
EQ0
Effect
L
L
L
H
~1.5 dB
L
L
H
H
~3 dB
L
H
L
H
~4.5 dB
L
H
H
H
~6 dB
H
L
L
H
~7.5 dB
H
L
H
H
~9 dB
H
H
L
H
~10.5 dB
H
H
H
H
~12 dB
EQ3
X
INPUTS
EQ2
EQ1
EQ0
X
X
L
* Default Setting is EQ = Off
Effect
OFF*
EMI Reduction Features
Des — Output Slew Rate Select (OS_CLKOUT/OS_DATA)
The parallel data outputs and clock outputs of the deserializer
feature selectable output slew rates. The slew rate of the
CLKOUT pin is controlled by the strap pin or register
OS_CLKOUT, while the data outputs (DO[23:0] and CO[3:1])
are controlled by the strap pin or register OS_DATA. When
OS_CLKOUT/DATA = HIGH, the maxium slew rate is select-
ed. When the OS_CLKOUT/DATA = LOW, the minimum slew
rate is selected. Use the higher slew rate when driving longer
traces or a heavier capacitive load.
Des — Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal ter-
mination. A capacitor may be placed on this pin for additional
common-mode filtering of the differential pair. This can be
useful in high noise environments for additional noise rejec-
tion capability. A 4.7 µF capacitor may be connected to this
pin to Ground.
Des — SSCG Generation — Optional
The Des provides an internally generated spread spectrum
clock (SSCG) to modulate its outputs. Both clock and data
outputs are modulated. This will aid to lower system EMI.
Output SSCG deviations to ±2% (4% total) at up to 100 kHz
modulations is available. Note: The device supports SSCG
function with CLK = 10 MHz to 65 MHz. When the CLK = 65
MHz to 75 MHz, it is required to disable SSCG function (SSC
[3:0] = 0000). See Table 5. This feature may be controlled by
external STRAP pins or by register.
TABLE 5. SSCG Configuration (LF_MODE = L) — Des Output
SSC3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
SSC[3:0] Inputs
LF_MODE = L (20 - 65 MHz)
SSC2
SSC1
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SSC0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
fdev (%)
NA
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
Result
fmod (kHz)
Disable
CLK/2168
CLK/1300
CLK/868
CLK/650
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