DS92LV2421 Datasheet, PDF (13/40 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

Symbol
Parameter
Conditions
t_DIH
Input Data - Hold Time,
Figure 4
CLKIN to DI[23:0], CI1, CI2, CI3
t_XZD
Ser Ouput Active to OFF Delay,
Figure 6
t_PLD
Serializer PLL Lock Time,
Figure 5
R_L = 100Ω
t_SD
Serializer Delay - Latency,
R_L = 100Ω
Figure 7
t_DJIT
Ser Output Total Jitter,
Figure 8
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern
λ_STXBW Serializer Jitter Transfer
Function -3 dB Bandwidth
δ_STX
Serializer Jitter Transfer
Function Peaking
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
t_RCP
CLK Output Period
t_RDC
CLK Output Duty Cycle
t_CLH
LVCMOS
Low-to-High
Transition Time, Figure 10
t_RCP = t_TCP
CLKOUT
V_DDIO = 1.71 to 1.89V,
C_L = 8 pF, OS_CLKOUT/
DATA = L
CLKOUT
V_DDIO = 1.71 to 1.89V
C_L = 8 pF, OS_CLKOUT/
DATA = H
V_DDIO = 3.0 to 3.6V
C_L = 8 pF, OS_CLKOUT/
DATA = L
V_DDIO = 3.0 to 3.6V
C_L = 8 pF, OS_CLKOUT/
DATA = H
t_CHL
LVCMOS
High-to-Low
Transition Time, Figure 10
V_DDIO = 1.71 to 1.89V
C_L = 8 pF, OS_CLKOUT/
DATA = L
CLKOUT
V_DDIO = 1.71 to 1.89V
C_L = 8 pF, OS_CLKOUT/
DATA = H
V_DDIO = 3.0 to 3.6V
C_L = 8 pF), OS_CLKOUT/
DATA = L
V_DDIO = 3.0 to 3.6V
C_L = 8 pF, OS_CLKOUT/
DATA = H
t_ROS
Data Valid before CLKOUT – V_DDIO = 1.71 to 1.89V
DO[23:0], CO1, CO2,
Set Up Time, Figure 14
C_L = 8 pF (lumped load) CO3
V_DDIO = 3.0 to 3.6V
C_L = 8 pF (lumped load)
t_ROH
Data Valid after CLKOUT –
V_DDIO = 1.71 to 1.89V
DO[23:0], CO1, CO2,
Hold Time, Figure 14
C_L = 8 pF (lumped load) CO3
V_DDIO = 3.0 to 3.6V
C_L = 8 pF (lumped load)
13
Min Typ Max Units
2
ns
8
15
ns
1.4
10
ms
144*T 145
ns
TBD
UI
TBD
kHz
TBD
dB
Min Typ Max Units
13.3
T
100
ns
45
50
55
%
2.5
3.5
ns
1.5
2.5
ns
2.5
3.5
ns
1.5
2.5
ns
2.5
3.5
ns
1.5
2.5
ns
2.5
3.5
ns
1.5
2.5
ns
TBD
0.5
UI
TBD
0.5
UI
TBD
0.5
UI
TBD
0.5
UI
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