DS92LV2421 Datasheet, PDF (22/40 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

Functional Description
The DS92LV2421 / DS92LV2422 chipset transmits and re-
ceives 24-bits of data and 3 control signals over a single serial
CML pair operating at 280 Mbps to 2.1 Gbps. The serial
stream also contains an embedded clock, video control sig-
nals and the DC-balance information which enhances signal
quality and supports AC coupling.
The Des can attain lock to a data stream without the use of a
separate reference clock source, which greatly simplifies sys-
tem complexity and overall cost. The Des also synchronizes
to the Ser regardless of the data pattern, delivering true au-
tomatic “plug and lock” performance. It can lock to the incom-
ing serial stream without the need of special training patterns
or sync characters. The Des recovers the clock and data by
extracting the embedded clock information, validating and
then deserializing the incoming data stream providing a par-
allel LVCMOS video bus to the display or ASIC/FPGA.
The DS92LV2421 / DS92LV2422 chipset can operate in 24-
bit color depth (with DE, HS, VS encoded within the serial data
stream). In 18–bit color applications, the three video control
signals maybe sent encoded within the serial bit stream (re-
strictions apply) along with six additional general purpose
signals.
Block Diagrams for the chipset are shown at the beginning of
this datasheet.
Data Transfer
The DS92LV2421 / DS92LV2422 chipset will transmit and
receive a pixel of data in the following format: C1 and C0 rep-
resent the embedded clock in the serial stream. C1 is always
HIGH and C0 is always LOW. The remaining 26 bit spaces
contain the scrambled, encoded and DC-Balanced serial da-
ta.
SER & DES OPERATING MODES AND REVERSE
COMPATIBILITY (CONFIG[1:0])
The DS92LV2421 / DS92LV2422 chipset is compatible with
other single serial lane Channel Link II or FPD-Link II devices.
Configuraiton modes are provided for reverse compatibility
with the DS90C241 / DS90C124 and also the DS90UR241 /
DS90UR124 by setting the respective mode with the CONFIG
[1:0] pins on the Ser or Des as shown in Table and Table. This
selection also determines whether the Control Signal Filter
feature is enabled or disabled in the Normal mode. These
configuration modes are selectable the the control pins only.
TABLE 1. DS92LV2421 Ser Modes
CONFIG1 CONFIG0 MODE
DES DEVICE
L
L
Normal Mode, DS92LV2422,
Control Signal DS92LV2412,
Filter disabled DS92LV0422,
DS92LV0412
L
H
Normal Mode, DS92LV2422,
Control Signal DS92LV2412,
Filter enabled DS92LV0422,
DS92LV0412
H
L
Reverse
DS90UR124,
Compatibility DS99R124
Mode
H
H
Reverse
DS90C124
Compatibility
Mode
DS92LV2422 Des Modes
CONFIG1 CONFIG0 MODE
SER DEVICE
L
L
Normal Mode, DS92LV2421,
Control Signal DS92LV2411,
Filter disabled DS92LV0421,
DS92LV0411
L
H
Normal Mode, DS92LV2421,
Control Signal DS92LV2411,
Filter enabled DS92LV0421,
DS92LV0411
H
L
Reverse
DS90UR241,
Compatibility
Mode
DS99R421
H
H
Reverse
DS90C241
Compatibility
Mode
VIDEO CONTROL SIGNAL FILTER — SER & DES
When operating the devices in Normal Mode, the Control Sig-
nals have the following restrictions:
• Normal Mode with Control Signal Filter Enabled: Control
Signal 1 and Control Signal 2 — Only 2 transitions per 130
clock cycles are transmitted, the transition pulse must be
3 parallel clocks or longer.
• Normal Mode with Control Signal Filter Disabled: Control
Signal 1 and Control Signal 2 — Only 2 transitions per 130
clock cycles are transmitted, no restriction on minimum
transition pulse.
• Control Signal 3 — Only 1 transition per 130 clock cycles
is transmitted , minimum pulse width is 130 clock cycles.
Control Signals are defined as low frequency signals with lim-
ited transition. Glitches of a control signal can cause a visual
error in display applications. This feature allows for the
chipset to validate and filter out any high frequency noise on
the control signals. See Figure.
SERIALIZER Functional Description
The Ser converts a wide parallel input bus to a single serial
output data stream, and also acts as a signal generator for
the chipset Built In Self Test (BIST) mode. The device can be
configured via external pins or through the optional serial
control bus. The Ser features enhance signal quality on the
link by supporting: a selectable VOD level, a selectable de-
emphasis signal conditioning and also the Channel Link II
data coding that provides randomization, scrambling, and DC
Balanacing of the data. The Ser includes multiple features to
reduce EMI associated with display data transmission. This
includes the randomization and scrambling of the data and
also the system spread spectrum clock support. The Ser fea-
tures power saving features with a sleep mode, auto stop
clock feature, and optional LVCMOS (1.8 V) parallel bus com-
patibility.
See also the Functional Description of the chipset's serial
control bus and BIST modes.
EMI Reduction Features
Data Randomization & Scrambling
Channel Link II Ser / Des feature a 3 step encoding process
which enables the use of AC coupled interconnects and also
helps to manage EMI. The serializer first passes the parallel
data through a scrambler which randomizes the data. The
randomized data is then DC balanced. The DC balanced and
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